Index of /files/Udemy/Udemy - High-Level Synthesis for FPGA, Part 2 - Sequential Circuits 2022-1/15. Project 2 UART/
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1. Introduction.mp4 02-Apr-2021 09:48 52391673
1. Introduction.srt 02-Apr-2021 09:48 2887
1.1 UART-Introduction-quiz-solution.pdf 02-Apr-2021 09:48 98859
2. Definition.mp4 02-Apr-2021 09:48 84913274
2. Definition.srt 02-Apr-2021 09:48 4421
2.1 P03S009L02-UART-Definition-Quiz-Solution.pdf 02-Apr-2021 09:48 158139
3. Design Structure and HLS.mp4 02-Apr-2021 09:49 44392950
3. Design Structure and HLS.srt 02-Apr-2021 09:49 2334
3.1 UART-DesignStructure-Quiz Solution.pdf 02-Apr-2021 09:49 87361
4. Transmitter-VitisHLS+Vivado.mp4 02-Apr-2021 09:49 206369245
4. Transmitter-VitisHLS+Vivado.srt 02-Apr-2021 09:49 12981
4.1 quiz.zip 02-Apr-2021 09:49 4869
4.2 TransmitterVitisHLSVivado-QuizSolution.pdf 02-Apr-2021 09:49 159652
4.3 UART-transmitter-code.zip 02-Apr-2021 09:49 50097
5. Receiver-VitisHLS+Vivado.mp4 02-Apr-2021 09:50 193728856
5. Receiver-VitisHLS+Vivado.srt 02-Apr-2021 09:50 12554
5.1 uart_receiver-code.zip 02-Apr-2021 09:50 15440
5.2 ReceiverVitisHLSVivado-quiz-solution.pdf 02-Apr-2021 09:50 337482
6. Exercises.html 02-Apr-2021 09:50 205
6.1 exercise01.zip 02-Apr-2021 09:50 45717
6.2 exercise02.zip 02-Apr-2021 09:50 7557
6.3 UART-Exercises-Solution.pdf 02-Apr-2021 09:50 189964