1 00:00:02,960 --> 00:00:06,780 Designing and debugging the new art receiver is the goal of this lecture. 2 00:00:09,170 --> 00:00:12,530 The receiver module receives a packet of data serially. 3 00:00:13,840 --> 00:00:20,290 Here we can see there are 10 bits of data containing it, start with a data bits and want to stop it. 4 00:00:21,370 --> 00:00:24,790 The circuit has two states idle and receive. 5 00:00:25,700 --> 00:00:32,810 Initially, the circuit is in the idle state waiting to receive this target when it receives the start 6 00:00:32,810 --> 00:00:36,900 with, it goes to the receiver state to receive a database. 7 00:00:38,770 --> 00:00:43,130 Are still a state accountable variable counts the number of received data. 8 00:00:44,000 --> 00:00:50,210 Finally, if the module receives the stop it, it goes back to the idle, ready for the next data packet. 9 00:00:55,150 --> 00:00:57,500 Let's have a look at the rest of our code initialised. 10 00:00:58,150 --> 00:01:03,510 First, we define an enumeration type to describe the circuit states they design. 11 00:01:03,520 --> 00:01:07,150 Top function has for arguments two inputs and outputs. 12 00:01:08,170 --> 00:01:14,590 The art underscore, Arax, is the input through which the module receives the asynchronous surreal 13 00:01:14,590 --> 00:01:14,880 data. 14 00:01:17,200 --> 00:01:23,470 They both underscore great underscore signal input gives regular policies that are used to sample data 15 00:01:23,590 --> 00:01:24,820 on the serial input. 16 00:01:26,540 --> 00:01:33,410 The data output carries the eight bit value received by the module, the valid underscore data output 17 00:01:33,830 --> 00:01:37,430 determines the validity of the value on the data output. 18 00:01:38,690 --> 00:01:45,860 Then we define three static variables that will be synthesized into registers in harder, the first 19 00:01:45,860 --> 00:01:47,900 one says the received data. 20 00:01:47,930 --> 00:01:53,870 It's the second one acts as a counter to count the number of receive bits. 21 00:01:55,380 --> 00:02:02,010 And the last one keeps track of the circuit state, then we define the temporary variables for a state 22 00:02:02,010 --> 00:02:04,040 and beat underscore count registered. 23 00:02:05,460 --> 00:02:08,730 Then we need the state machine to implement the module behavior. 24 00:02:09,860 --> 00:02:16,100 After that, we should update registers and assign values to Doubt's, as I mentioned earlier, the 25 00:02:16,100 --> 00:02:19,400 state machine has two estates idle and Rosie. 26 00:02:24,490 --> 00:02:28,780 In the final state, the circuit is only waiting to receive the circuit. 27 00:02:29,710 --> 00:02:35,410 When it receives a zero on the fourth and the score asks input, it goes to the receiver state to get 28 00:02:35,410 --> 00:02:39,640 the data, it's in the receiver state if the board rate is zero. 29 00:02:41,070 --> 00:02:45,120 It stays in the reserve state waiting for the next sampling time. 30 00:02:46,890 --> 00:02:53,880 When the board right signal is one, it samples the art, our signal and says that in the dirigiste 31 00:02:54,690 --> 00:02:55,890 and increment the count. 32 00:02:57,710 --> 00:03:05,150 After finishing the database, it samples the subject that should be one, if it is one, then it activates 33 00:03:05,300 --> 00:03:08,720 the valid data local variable and goes to the Iowa State. 34 00:03:14,510 --> 00:03:19,760 Let's review the whole design, the basics, the board is connected to a computer through the you are 35 00:03:19,760 --> 00:03:25,400 data USB port when we press a key in a surreal terminal program on the computer. 36 00:03:26,530 --> 00:03:32,590 The corresponding ASCII code will be sent to the board to receive design inside the fridge, receives 37 00:03:32,590 --> 00:03:35,530 the code and shows that on a seven segment display. 38 00:03:39,940 --> 00:03:44,320 There is a design inside the FPGA consists of three epis. 39 00:03:47,200 --> 00:03:49,960 The first on the main one is the receiver IP. 40 00:03:52,050 --> 00:03:58,890 In addition, we need the both right signal generator and then IP to display and ASCII character on 41 00:03:58,890 --> 00:03:59,970 a seven segment display. 42 00:04:04,260 --> 00:04:09,540 Now let's go to the white Essentialists and designed ipis, the first one is a display of. 43 00:04:10,430 --> 00:04:16,510 Open the white to and create a new project with the name of serial underscore display, Dasch want to 44 00:04:17,420 --> 00:04:22,880 choose a serial underscored display as a design type function and select the basis to report as a target 45 00:04:22,880 --> 00:04:23,780 FPGA platform. 46 00:04:33,130 --> 00:04:36,550 Download the design, 5:00 a.m. to the creative project. 47 00:04:47,000 --> 00:04:53,740 Open the design here, it contains an array of the same segment codes for characters from zero to F. 48 00:04:55,560 --> 00:05:01,530 Because of the seven segment restriction in showing all characters, we only show these characters on 49 00:05:01,530 --> 00:05:02,420 this one segment. 50 00:05:03,990 --> 00:05:06,480 And for any other character, we shall see. 51 00:05:16,190 --> 00:05:21,860 Open the design file, it receives an ASCII code and convert that to the corresponding seven segment 52 00:05:21,860 --> 00:05:22,190 code. 53 00:05:23,390 --> 00:05:30,350 The function askey to some segment, does this task synthesize the code and generate the corresponding 54 00:05:30,350 --> 00:05:31,070 artier like. 55 00:06:01,720 --> 00:06:07,150 Now, let's describe the yard, receive our invite to create a new White House project with the name 56 00:06:07,150 --> 00:06:09,120 of your art underscore receiver dash. 57 00:06:09,130 --> 00:06:15,690 White physicians choose the art on the receiver as a top function name and select the basis three board 58 00:06:15,700 --> 00:06:17,140 as a target FPGA platform. 59 00:06:27,390 --> 00:06:31,020 Download the design and test files and add them to the project's. 60 00:06:40,640 --> 00:06:44,190 Open the design source file and inspect the design top function. 61 00:07:18,190 --> 00:07:24,970 Then open the open source park, the main function calls are designed to function several times each 62 00:07:24,970 --> 00:07:31,870 time a single bit of Dewart packet containing the ASCII code of the character is given to the design. 63 00:07:32,980 --> 00:07:39,940 Now, let's perform the simulation and check out the output confirms the design functionality. 64 00:07:42,800 --> 00:07:47,480 Now, we should perform the high level syntheses and generate the corresponding IP. 65 00:08:04,570 --> 00:08:08,410 Now we are going to connect the lips together in Nevada project. 66 00:08:11,260 --> 00:08:17,770 Create a new we, the project with the name of you art, underscore receiver dashboard and choose the 67 00:08:17,770 --> 00:08:19,820 basis to report as a target FPGA. 68 00:08:34,920 --> 00:08:36,240 Create a new blog design. 69 00:08:50,160 --> 00:08:52,950 And at three ipis today, we want a repository. 70 00:08:54,170 --> 00:08:59,060 All right, generator, surreal display, and you are receiving. 71 00:09:00,390 --> 00:09:04,130 You can find some of the ipis in the resources folder attached to this lecture. 72 00:09:05,700 --> 00:09:09,310 And ipis into the design area and connect them together. 73 00:10:48,550 --> 00:10:54,810 Download the content fine from the resources folder attached to this lecture and add that to the project, 74 00:10:55,430 --> 00:11:01,090 how we look at the conference, then generate the FPGA bitstream and program the board. 75 00:12:22,270 --> 00:12:25,960 Run a terminal program on the computer that is connected to your board. 76 00:12:27,280 --> 00:12:34,780 You can use the Terrytown program, go to the set up serial port, choose the proper comport corresponding 77 00:12:34,780 --> 00:12:35,500 to your board. 78 00:12:36,890 --> 00:12:41,750 Select ninety six hundred as they speak and keep the default values for other options. 79 00:12:43,530 --> 00:12:47,520 Now, why the terminal program is running Presta a character. 80 00:12:49,270 --> 00:12:52,360 You should see the character on the some of the segment on your board. 81 00:12:54,590 --> 00:13:01,290 Note that the terminal doesn't show anything, however, you are using its API to communicate with the 82 00:13:01,670 --> 00:13:02,780 receiver on the board. 83 00:13:07,310 --> 00:13:13,040 Now, let's perform the runtime debugging to investigate the timing behind the data transfer between 84 00:13:13,040 --> 00:13:19,760 the PC terminal program and the board, if you want to project and add the IP to the design. 85 00:13:20,970 --> 00:13:26,750 We are going to monitor two signals you can't underscoring and the Boatwright's signal. 86 00:13:30,680 --> 00:13:36,230 Our trigger condition is when the start, it appears on the chart, underscore our signal. 87 00:13:38,060 --> 00:13:42,830 Double click on the IP there, customized IP window will appear. 88 00:13:44,780 --> 00:13:48,860 In the general options to choose negative as the monitor type. 89 00:13:50,130 --> 00:13:53,580 Then set two for the number of props. 90 00:13:56,120 --> 00:14:03,470 Choose one hundred and thirty one thousand seventy two as a sample data depth, now go to the pro tab. 91 00:14:04,500 --> 00:14:09,590 Select the data on trigger for the first probe and only data for the second probe. 92 00:14:10,590 --> 00:14:13,460 Press OK, to close their customized IP window. 93 00:14:14,870 --> 00:14:21,110 Now, make the connections, first of all, connect the clock signal, then connect the dots, connect 94 00:14:21,110 --> 00:14:26,770 the zero to the earth, underscore our signal unproven to the border signal. 95 00:14:27,750 --> 00:14:30,900 Then generate FPGA bitstream and programmed the world. 96 00:15:41,330 --> 00:15:47,810 The hardware manager window should appear, go to the trigger, set up top and define the trigger boolean 97 00:15:47,810 --> 00:15:53,750 expression for this purpose, click on the plus icon and select the only signal on the list. 98 00:15:54,890 --> 00:16:01,010 We should start sampling when we receive a zero, and you are to underscore our signal, so change the 99 00:16:01,010 --> 00:16:03,500 value to one to zero transition. 100 00:16:06,500 --> 00:16:13,240 Now go to the setting tab on the left, make sure that the trigger position in window is zero. 101 00:16:15,470 --> 00:16:20,240 Then in the south, stop, click on the wrong trigger for this L.A. icon. 102 00:16:21,720 --> 00:16:26,690 Dialla Core is monitoring the art underscore IREX for the triggering condition. 103 00:16:28,710 --> 00:16:33,510 Now, in the surreal terminal program, type the character A. 104 00:16:35,580 --> 00:16:43,060 As soon as you type the character, Dialla receives the following edge on the art underscore arcs and 105 00:16:43,060 --> 00:16:45,270 it starts the data sampling process. 106 00:16:47,160 --> 00:16:49,590 You will see the signals on the way form viewer. 107 00:16:52,770 --> 00:16:56,070 Check the waveforms and make sure that you understand the time. 108 00:17:06,380 --> 00:17:12,950 As this video is the last lecture explaining how to design your transmitter and receiver IPIS in the 109 00:17:12,950 --> 00:17:18,410 next lecture will give you a couple of exercises to master what you have learned throughout this section. 110 00:17:20,710 --> 00:17:22,280 These are our takeaway messages. 111 00:17:22,720 --> 00:17:29,050 It will stay there for them along with the counter can model if you are to receive our module in the 112 00:17:29,050 --> 00:17:34,810 falling edge of the new earth, receive our signal can be used to trigger Iola for monitoring that you 113 00:17:34,810 --> 00:17:36,210 are timing in inveigle. 114 00:17:42,020 --> 00:17:48,530 Now, the police question monitored the data output port of the you are receiving IP during runtime 115 00:17:48,530 --> 00:17:49,070 debugging.