Index of /files/Udemy/Udemy - High-Level Synthesis for FPGA, Part 2 - Sequential Circuits 2022-1/

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1. Prologue/                                       02-Apr-2021 09:18                   -
10. Function Pipelining/                           02-Apr-2021 09:40                   -
11. Seven Segments/                                02-Apr-2021 09:42                   -
12. PMOD/                                          02-Apr-2021 09:43                   -
13. Interface Synthesis/                           02-Apr-2021 09:46                   -
14. Project 1 Digital Dice/                        02-Apr-2021 09:48                   -
15. Project 2 UART/                                02-Apr-2021 09:50                   -
16. Project 3 Stepper Motor/                       02-Apr-2021 09:53                   -
2. HWSW Setup/                                     02-Apr-2021 09:20                   -
3. D Flip-Flop (DFF)/                              02-Apr-2021 09:24                   -
4. Single Cycle Design Flow/                       02-Apr-2021 09:28                   -
5. Testbench 01/                                   02-Apr-2021 09:30                   -
6. State Machine/                                  02-Apr-2021 09:32                   -
7. Utilities/                                      02-Apr-2021 09:35                   -
8. Vending Machine/                                02-Apr-2021 09:37                   -
9. Integrated Logic Analyzer (ILA)/                02-Apr-2021 09:38                   -