1 00:00:02,200 --> 00:00:08,260 How can we describe the transmitter module invited, such as this lecture will answer this question. 2 00:00:11,300 --> 00:00:16,750 First of all, let's have a big picture of the final design involved and IPPs involved. 3 00:00:17,990 --> 00:00:24,620 We have your transmitter IP described in necklace, then a border generator provides the Boatwright's 4 00:00:24,620 --> 00:00:30,950 signal, the AP data input is connected to the light switches on the board and finally and the bouncer 5 00:00:30,950 --> 00:00:34,980 and a pulse generator connect the start to a push button on the board. 6 00:00:35,720 --> 00:00:37,610 Let's talk about the you are transmitter. 7 00:00:40,490 --> 00:00:46,550 The main task of our transmitter, IP, is sending out 10 bits of data, one by one, and receiving 8 00:00:46,550 --> 00:00:48,470 a pulse on the board right signal. 9 00:00:49,490 --> 00:00:56,150 Initially, the design is waiting for a pulse on a starting point to begin its task, therefore, the 10 00:00:56,150 --> 00:00:59,510 design would have to sit idle and transmit. 11 00:01:00,720 --> 00:01:06,630 And I illustrate the signal is waiting for a pulse on the starting and in the transmitter state, it 12 00:01:06,630 --> 00:01:08,700 sends out one bit of the data. 13 00:01:09,090 --> 00:01:14,940 Whenever it receives a pulse on the board right signal, the circuit stays in the transmitter state 14 00:01:15,030 --> 00:01:22,110 until it sends out all the 10 bits of data a can help to determine the time the circuit should go to 15 00:01:22,110 --> 00:01:22,980 the idle state. 16 00:01:25,930 --> 00:01:32,020 Let's describe the circuit in each of us, first of all, we define an enumeration data type to represent 17 00:01:32,020 --> 00:01:39,360 the circuit states, then we should define the top function that has three inputs and one output to 18 00:01:39,370 --> 00:01:42,190 static variables should be defined in the design. 19 00:01:42,990 --> 00:01:47,700 The first one keeps the circuit state and the other is used as the counter. 20 00:01:49,010 --> 00:01:55,040 Two temporary variables are defined to save the intermediate values of state and top function output. 21 00:01:58,720 --> 00:02:07,420 The start with date of its unstopped or concatenated to form a simple 10 with one, then we have the 22 00:02:07,420 --> 00:02:09,370 state machine with two states. 23 00:02:13,970 --> 00:02:18,740 After that, we should modify the state and the U.S. on this 46 variables. 24 00:02:23,530 --> 00:02:29,560 If the circuit receives a single pulse on the starting point when it is in the idle state, it goes 25 00:02:29,560 --> 00:02:36,730 to to transmit state, otherwise it stays in the middle seat in the transmit to state, the behavior 26 00:02:36,730 --> 00:02:39,160 of the design is a little bit complex. 27 00:02:39,320 --> 00:02:41,740 First, it checks the bold red signal. 28 00:02:42,040 --> 00:02:50,170 If it is one, the circuit should send out one bit of the data value and increment the counter and stay 29 00:02:50,170 --> 00:02:51,370 in the transmit state. 30 00:02:51,730 --> 00:02:56,050 However, when the counter is ten, the state machine goes to the idle state. 31 00:02:56,800 --> 00:03:03,670 If the bold red signal is zero, then the circuit sends out the last send data of it to keep the output 32 00:03:03,670 --> 00:03:06,880 stable and stays in the transmit state. 33 00:03:10,450 --> 00:03:17,890 The basis the report includes a USB port bridge attached to the Connector J4 that allows you to use 34 00:03:17,890 --> 00:03:24,690 PC applications to communicate with the board using standard windows, comport commands to on board 35 00:03:24,700 --> 00:03:31,660 a satis LEDs, provide visual feedback on the traffic flowing through the port, the transmitter, the 36 00:03:31,800 --> 00:03:34,830 LDA and the receiver LDA. 37 00:03:35,990 --> 00:03:40,540 This figure shows the board configuration that hosts you are transmitter design. 38 00:03:41,410 --> 00:03:47,590 The starting point is connected to the push button, as I mentioned earlier, the USPI data connection 39 00:03:47,620 --> 00:03:51,100 also can be used as the report on this particular. 40 00:03:54,080 --> 00:04:00,140 Now, let's describe the circuit, invite Essentialists, we should describe to ipis the Boulder generator 41 00:04:00,440 --> 00:04:01,460 and the transmitter. 42 00:04:05,210 --> 00:04:10,910 Let's first describe the board, regenerate, create a new white essentialist project with the name 43 00:04:10,910 --> 00:04:16,940 of board, underscore great underscore generator, dash white Essentialists and select the board regenerator 44 00:04:16,940 --> 00:04:21,800 as a top function name and choose the basis to board as a target FPGA platform. 45 00:04:31,450 --> 00:04:36,580 Download the design and test bench files from the resources folder attached to this lecture and add 46 00:04:36,580 --> 00:04:37,540 them to the project. 47 00:04:45,860 --> 00:04:52,520 Open the design source, why this design is very similar to the single cycle regular process design 48 00:04:52,640 --> 00:05:00,620 explained in the utility section, except here the parts per year is ten thousand four hundred and sixty 49 00:05:01,340 --> 00:05:08,390 to generate pulses with the frequency of ninety six hundred hertz or ninety six hundred pulses per second, 50 00:05:09,020 --> 00:05:10,460 which is our selected. 51 00:05:10,460 --> 00:05:12,500 You are portrayed in this project. 52 00:05:12,890 --> 00:05:14,270 For the sake of simplicity. 53 00:05:14,610 --> 00:05:18,710 We can assign 20 to the board rate number just for simulation. 54 00:05:19,820 --> 00:05:25,450 Then we can perform the simulation to make sure the code functionality is correct. 55 00:05:44,870 --> 00:05:50,780 After that, we should restore the proper value to the boards right number and synthesize the code and 56 00:05:50,780 --> 00:05:52,340 generate the corresponding IP. 57 00:07:13,980 --> 00:07:19,680 Now create another white, such a site with the name of your art underscore transmitter that Schweitzer 58 00:07:20,850 --> 00:07:26,790 and tools that you are a transmitter as a top functionary, then select the basis three board as a target 59 00:07:26,790 --> 00:07:27,330 FPGA. 60 00:07:35,500 --> 00:07:40,840 Download the design and test bench fines from the resources folder attached to this lecture and add 61 00:07:40,840 --> 00:07:41,950 them to the project's. 62 00:07:49,210 --> 00:07:54,520 Open the design Sourcefire, it contains the top function and description explained earlier in the structure. 63 00:08:32,280 --> 00:08:39,060 Have a look at the Test match for the sea main function assigns the value of zero one zero zero zero 64 00:08:39,060 --> 00:08:43,350 zero zero one to the data variable as the input parallel data. 65 00:08:43,740 --> 00:08:50,490 Then it calls the design top function several times to generate the board's pulses board rate signal 66 00:08:50,490 --> 00:08:54,090 variable alternates between zero and one in the form. 67 00:08:58,610 --> 00:09:05,330 Perform the simulation and check it out here, we can check the design functionality and not the timing. 68 00:09:16,900 --> 00:09:20,890 Then perform the high level syntheses and TLC called Simulation. 69 00:10:19,930 --> 00:10:25,930 In the way for future, check the outputs and make sure that the output sequence is correct here is 70 00:10:25,930 --> 00:10:32,800 still we cannot check the timing as the design requires Boldrin generator IP, which is available during 71 00:10:32,800 --> 00:10:35,170 Logic's sentences in the regard on project. 72 00:10:53,290 --> 00:10:56,620 Export our IP to be used in environmental projects. 73 00:11:21,980 --> 00:11:28,250 Now let's create a new revival project with the name of your art underscore transmitter Dash Willott 74 00:11:28,700 --> 00:11:31,580 and select bassist reborn as a Target FPGA platform. 75 00:11:53,130 --> 00:12:00,210 Curate a new blog design and ad for Ipis to deliver the repository, the bouncer, pulse generator, 76 00:12:00,690 --> 00:12:03,660 Boldrin generator and the user transmit. 77 00:12:33,710 --> 00:12:38,360 Instantiate the IPS and connect them together and change the name properly. 78 00:14:10,550 --> 00:14:14,330 Download the file and add that to the device, the project. 79 00:14:30,470 --> 00:14:32,950 Generate FPGA bitstream and programmable. 80 00:15:03,210 --> 00:15:08,130 On your computer connected to the bases, report on a serial terminal program. 81 00:15:09,980 --> 00:15:11,360 Such as Turtur. 82 00:15:12,430 --> 00:15:15,040 You can download that at this address. 83 00:15:16,550 --> 00:15:24,140 Go to set up serial port, then to the proper compost that is corresponding to your birth connection. 84 00:15:25,210 --> 00:15:31,770 Select ninety six hundred as the speed and keep the default values for other options and press. 85 00:15:31,780 --> 00:15:36,040 OK, now the terminal is ready to receive data from your board. 86 00:15:39,090 --> 00:15:46,930 Subtask called up a character on the slide switches, the code is zero one zero zero zero zero zero 87 00:15:46,930 --> 00:15:47,160 one. 88 00:15:56,100 --> 00:15:57,960 Then press the push button. 89 00:15:59,730 --> 00:16:03,620 You should see the character inside the terminal running on your computer. 90 00:16:04,890 --> 00:16:08,790 Sadowsky called for other letters and numbers and checked the terminals. 91 00:16:19,140 --> 00:16:26,250 To understand the design timing, let's follow the runtime debugging mechanism using IP, explain throughout 92 00:16:26,250 --> 00:16:29,660 this course and dial IP to the design. 93 00:16:30,180 --> 00:16:36,060 Now double click on that to customize the IP, select the native as the monitor type. 94 00:16:36,720 --> 00:16:38,010 Consider three Poirot's. 95 00:16:39,420 --> 00:16:46,530 Notes that as each You Are Baudry period contains ten thousand two hundred sixteen clock cycles. 96 00:16:47,680 --> 00:16:54,550 Then for sending 10 minutes over art collection, we need at least ten thousand two hundred and sixteen, 97 00:16:54,550 --> 00:16:55,920 multiply ten samples. 98 00:16:56,740 --> 00:17:02,950 Therefore in the sample data depth option, choose one hundred thirty one thousand seventy two. 99 00:17:03,870 --> 00:17:08,970 Now go to the proper tab and select one trigger and to date Uprose. 100 00:17:10,060 --> 00:17:12,310 Close the window and make the connections. 101 00:17:13,420 --> 00:17:18,710 First of all, connect the clock signal, then connect zero to the pulse generator. 102 00:17:19,630 --> 00:17:24,280 Note that this probe is a trigger signal that triggers the sampling process. 103 00:17:25,430 --> 00:17:32,660 Then connect one to the board, regenerator out and finally connect the probe, two to the transmitter 104 00:17:32,660 --> 00:17:36,740 output now generated FPGA bitstream and programmed aboard. 105 00:18:09,130 --> 00:18:14,940 After programming the board, you should see the isolator perspective in the regard idee. 106 00:18:17,470 --> 00:18:23,590 In the three years, a window click on the plus icon and select the only trigger signal in the least, 107 00:18:24,040 --> 00:18:25,880 change the value from X to one. 108 00:18:26,680 --> 00:18:33,760 Now go to the setting, S.W. underscore Ilea, underscore one tab and make sure that the trigger position 109 00:18:33,910 --> 00:18:35,220 window option is Zeil. 110 00:18:36,790 --> 00:18:43,330 Now go to the status, stop and press on the wrong trigger for this, ERICO, now on the board, said 111 00:18:43,340 --> 00:18:47,830 the character Askey code on the slide switches and pressed our push button. 112 00:18:48,710 --> 00:18:55,220 Dialogue will start sampling and show the waveforms on its way, form viewer, check the timing and 113 00:18:55,220 --> 00:18:56,360 value correctness. 114 00:20:04,030 --> 00:20:08,470 The next lecture explains how to design the yuan's receiver module in Etchells. 115 00:20:13,060 --> 00:20:18,900 These are our takeaway messages, a counter and a state machine between states can model if you are 116 00:20:18,910 --> 00:20:24,550 transmitter, it can be used to monitor the you are transmitter signals are the on. 117 00:20:29,240 --> 00:20:35,240 Now, the quiz question modified the code to follow our coding style, explained throughout the course.