Index of /files/Udemy/Udemy - High-Level Synthesis for FPGA, Part 2 - Sequential Circuits 2022-1/13. Interface Synthesis/
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1. Introduction.mp4 02-Apr-2021 09:43 84609529
1. Introduction.srt 02-Apr-2021 09:43 4759
10. Exercises.html 02-Apr-2021 09:46 268
2. SCII Proc&Cons.mp4 02-Apr-2021 09:44 67788521
2. SCII Proc&Cons.srt 02-Apr-2021 09:44 3969
2.1 SingleCycleProc^0Cons-Quiz-Solution.pdf 02-Apr-2021 09:44 126521
3. Definition.mp4 02-Apr-2021 09:44 98737064
3. Definition.srt 02-Apr-2021 09:44 5678
3.1 P03S02L02-Definition-Quiz-Solution.pdf 02-Apr-2021 09:44 99799
4. Interface Synthesis.mp4 02-Apr-2021 09:44 84895981
4. Interface Synthesis.srt 02-Apr-2021 09:44 5359
4.1 P03S02L04-Interface SynthesisQuiz Solution.pdf 02-Apr-2021 09:44 225230
5. Block Level ap_ctrl_hs.mp4 02-Apr-2021 09:45 81337001
5. Block Level ap_ctrl_hs.srt 02-Apr-2021 09:45 4636
5.1 P03S02L05-BlockLevel-ap_ctrl_hs-Quiz Soluti..> 02-Apr-2021 09:45 179944
6. Block Level ap_ctrl_hs vitis-hls.mp4 02-Apr-2021 09:45 218492479
6. Block Level ap_ctrl_hs vitis-hls.srt 02-Apr-2021 09:45 11063
6.1 BlockLevel-ap_ctrl_hs_vitis-hls-Quiz Soluti..> 02-Apr-2021 09:45 86044
6.2 BlockLevel-ap_ctrl_hs_vitis-hls.zip 02-Apr-2021 09:45 52519
7. Port Level ap_vld.mp4 02-Apr-2021 09:45 57189025
7. Port Level ap_vld.srt 02-Apr-2021 09:45 3048
7.1 P03S02L06-PortLevel-ap_vld-quiz-Solution.pdf 02-Apr-2021 09:45 171616
7.2 adder_vitishls.zip 02-Apr-2021 09:45 2137
8. Port Level ap_ack.mp4 02-Apr-2021 09:46 52583836
8. Port Level ap_ack.srt 02-Apr-2021 09:46 2850
8.1 adder_vitishls.zip 02-Apr-2021 09:46 2135
8.2 P03S02L07-PortLevel-ap_ack-quiz-solution.pdf 02-Apr-2021 09:46 171115
9. Port Level ap_hs.mp4 02-Apr-2021 09:46 54902469
9. Port Level ap_hs.srt 02-Apr-2021 09:46 2828
9.1 adder_vitishls.zip 02-Apr-2021 09:46 2133
9.2 P03S02L08-PortLevel-ap_hs-Quiz-Solution.pdf 02-Apr-2021 09:46 164498