1 00:00:03,490 --> 00:00:10,240 How can we show the behavior of the black level interface, ABC, TRL, X in practice, this lecture 2 00:00:10,390 --> 00:00:16,580 will take an example of a simple floating point accumulator to represent the signaling of the APC TRL 3 00:00:16,840 --> 00:00:20,860 as interface in action by using an integrated logic analyzer. 4 00:00:24,770 --> 00:00:31,420 Let's consider the floating point accumulator circuit as an example of a multi cycle designing this 5 00:00:31,430 --> 00:00:36,880 circuit receives a sequence of floating point numbers and accumulates that as its output. 6 00:00:37,250 --> 00:00:43,490 For example, this figure shows the output generated for this sequence of input as shown in this diagram. 7 00:00:43,610 --> 00:00:44,770 Our design is simple. 8 00:00:45,080 --> 00:00:47,960 It consists of a floating point adder and the register. 9 00:00:51,220 --> 00:00:56,590 Now, let's describe the floating point accumulator initialised the top function, receives an input 10 00:00:56,590 --> 00:01:04,140 and generates an out, we need a static variable to save the previous results, then we need the addition. 11 00:01:04,480 --> 00:01:06,670 And finally sending out the results. 12 00:01:06,700 --> 00:01:13,000 As the state register provides the output directly, we should ensure that the center system does not 13 00:01:13,000 --> 00:01:17,950 optimize that and merge it with other registers in the article design after synthesis. 14 00:01:18,490 --> 00:01:23,960 For this purpose, we can add the volatile modifier to the static variable declaration. 15 00:01:24,340 --> 00:01:26,290 Now we should add the interfaces. 16 00:01:28,040 --> 00:01:34,130 First of all, let's add the module level interface here, the ABC, TRL X is selected. 17 00:01:35,320 --> 00:01:40,130 We will control the hardware module execution and run that whenever an input value is ready. 18 00:01:40,780 --> 00:01:43,120 Then we have the argument interfaces. 19 00:01:43,420 --> 00:01:46,090 Also, we apply the pipeline optimization program. 20 00:01:46,780 --> 00:01:51,450 However, because of the data dependency on the code, the function cannot be pipelined. 21 00:01:51,640 --> 00:01:53,630 We will see this later in this lecture. 22 00:01:59,860 --> 00:02:05,650 Note that instead of using the volatile modifier, we can guide the tool to implement the output with 23 00:02:05,650 --> 00:02:11,950 a dedicated register for this purpose, we should add the keyboard register at the end of the output 24 00:02:11,950 --> 00:02:13,000 interface definition. 25 00:02:17,320 --> 00:02:19,970 This slide shows the final design involved. 26 00:02:20,680 --> 00:02:26,980 We have the float accumulator IP, then we have another IP that receives the accumulator output and 27 00:02:26,980 --> 00:02:29,020 shows that on the seven segment display. 28 00:02:29,560 --> 00:02:37,180 However, as we cannot generate floating point numbers easily on the board using the basic input mechanisms 29 00:02:37,180 --> 00:02:42,130 such as light switches, we need another IP to generate a sequence of floating point numbers. 30 00:02:42,340 --> 00:02:49,450 This IP generates a floating point number whenever we requested that through its input by a single cycle 31 00:02:49,450 --> 00:02:51,970 pulse, which a push button will generate. 32 00:02:53,340 --> 00:02:59,640 Therefore, we needed the bouncer and Pulcinella authorities also, we use the AP done output of the 33 00:02:59,640 --> 00:03:02,910 number generator IP to start the accumulator task. 34 00:03:08,670 --> 00:03:10,650 Let's have a look at the number generator type. 35 00:03:11,810 --> 00:03:18,440 It has an area of 10 numbers which sends out one of them when it's requested, the top function has 36 00:03:18,440 --> 00:03:19,940 one input and output. 37 00:03:21,810 --> 00:03:27,690 To keep track of the air index, we need a static variable, then we define the register to keep the 38 00:03:27,690 --> 00:03:30,990 generated output stable, to be used by the downstream. 39 00:03:32,250 --> 00:03:34,830 Then the code checks to generate input. 40 00:03:35,070 --> 00:03:41,280 If it's one, it uses the index register to access a number in the area and send that out. 41 00:03:41,580 --> 00:03:48,540 Then it increments the index and makes sure that it is between zero and nine as the defined area has 42 00:03:48,540 --> 00:03:49,650 only 10 elements. 43 00:03:50,340 --> 00:03:54,470 The AP interface is also assigned to the module. 44 00:03:55,630 --> 00:03:57,610 Now let's see the design in action. 45 00:04:00,190 --> 00:04:03,460 Let's first ride the float accumulator, invite socialists. 46 00:04:08,360 --> 00:04:15,110 For this purpose, open the White House and create a new project with the name of Fallowed underscore 47 00:04:15,110 --> 00:04:15,810 accumulator. 48 00:04:16,380 --> 00:04:21,190 That's what researchers said the top function name to float, underscore, accumulate. 49 00:04:22,260 --> 00:04:26,430 And don't forget to select the basis to report as a target FPGA platform. 50 00:04:38,900 --> 00:04:44,570 Download the design and test bench files from the resources folder attached to this lecture and add 51 00:04:44,570 --> 00:04:46,010 them to the created project. 52 00:04:55,460 --> 00:05:01,700 Often the design they're fighting, it defines the data type macro, which here is float. 53 00:05:02,680 --> 00:05:06,530 Then open the design source file and have a look at the code. 54 00:05:07,360 --> 00:05:10,240 This is the code that we saw earlier in this lecture. 55 00:05:12,930 --> 00:05:18,420 Open the first page header for it defines the end macro to represent the value of 10. 56 00:05:19,400 --> 00:05:25,700 Now, let's look at a test source, Sourcefire, it defines a software implementation for the design 57 00:05:25,790 --> 00:05:29,330 as the golden model then in the main function. 58 00:05:30,450 --> 00:05:38,910 An area of 10 floating point value is declared, then it calls the design and times and prints out doubts. 59 00:05:39,330 --> 00:05:43,250 After that, it checks the final result with that of the Golden Model. 60 00:05:44,040 --> 00:05:45,510 Let's perform the simulation. 61 00:05:58,200 --> 00:06:01,470 The result confirms the design functionality, correctness. 62 00:06:02,860 --> 00:06:07,480 After finishing the simulation, successfully performed a high level synthesis. 63 00:06:25,240 --> 00:06:32,200 The result shows that the design is not pipelined properly as initiation in Tarawallie is, the main 64 00:06:32,200 --> 00:06:39,550 reason is the data dependency between two consecutive function calls on the ATC underscore state register. 65 00:06:42,630 --> 00:06:47,050 Export RTL IP to be used later in the project. 66 00:06:47,610 --> 00:06:53,550 Now let's describe the floating point display driver invited suchness create a new white essentialist 67 00:06:53,550 --> 00:06:58,910 project with the name of display underscore float Dasch White Essentialists for the basis Thibaut. 68 00:07:14,540 --> 00:07:17,690 Download the design files and add that to the created project. 69 00:07:24,610 --> 00:07:32,530 Open the design source finds the display driver function utilizes a four state FSM to show four digits 70 00:07:32,530 --> 00:07:34,030 on the seven segment displays. 71 00:07:35,810 --> 00:07:38,660 They're designed to function, receives a floating point number. 72 00:07:39,850 --> 00:07:46,810 Exact digits and calls the display underscore driver function to generate the corresponding sound segment 73 00:07:46,810 --> 00:07:51,640 signals the design, assumes that the number has a two digit fraction of what? 74 00:07:53,570 --> 00:07:56,210 Synthesize the Code and Export Authority like. 75 00:08:03,030 --> 00:08:06,410 We should design another IPO to generate floating point numbers. 76 00:08:07,640 --> 00:08:13,420 Create a new White House project with the name of generate underscore, fallowed, underscore, no dash 77 00:08:13,430 --> 00:08:15,380 white assiduous for the base's triple. 78 00:08:34,530 --> 00:08:37,680 Download the design files and add them to the project's. 79 00:08:52,470 --> 00:08:58,560 Have a look at the design header and Sourcefire, we saw them earlier in this lecture, synthesize the 80 00:08:58,560 --> 00:09:00,390 code and export the artillery. 81 00:09:03,930 --> 00:09:09,690 Now, generically, we want a project with the name of float underscore accumulator that we want. 82 00:09:24,090 --> 00:09:27,350 Create a new block design. 83 00:09:39,080 --> 00:09:41,630 And five ipis to divide the repository. 84 00:09:55,760 --> 00:09:58,130 The bouncer display float. 85 00:09:59,390 --> 00:10:07,310 Float accumulator generates float numbers and pulse generator ipis instantiate the IPS and connect them 86 00:10:07,310 --> 00:10:07,750 together. 87 00:12:31,190 --> 00:12:37,970 And your IP for monitoring some of the design signals customise the IP by adding seven probes to the 88 00:12:38,540 --> 00:12:42,290 IP, then connect that to the design signals. 89 00:15:26,410 --> 00:15:32,150 Downloaded this on Konstantine and add that to the project, then generic, that refuge's. 90 00:17:10,170 --> 00:17:16,350 Defined the trigger boolean expression and a start ilf for sampling, press the up push button on the 91 00:17:16,350 --> 00:17:19,800 board and examine the signals on Dialla waveform window. 92 00:17:20,190 --> 00:17:24,750 Try to understand the block level interface signals in the Ayalew waveforms. 93 00:17:43,230 --> 00:17:46,290 Play with the board and check the design functionality. 94 00:18:31,820 --> 00:18:37,670 The next letter, we look at airport level interface that introduces a validated signal attached to 95 00:18:37,670 --> 00:18:38,440 each argument. 96 00:18:42,600 --> 00:18:48,570 These are our takeaway messages, the high level synthesis process may optimize the code by merging 97 00:18:48,570 --> 00:18:51,650 or removing registers and variables defined in the code. 98 00:18:52,140 --> 00:18:57,900 If you want to keep a register, then use a volatile modifier when you declare the corresponding variable. 99 00:18:58,800 --> 00:19:05,400 Describing hardware modules in Etchells to generate input data for a design can be helpful in several 100 00:19:05,400 --> 00:19:06,180 occasions. 101 00:19:10,090 --> 00:19:16,330 Now, the police question, what is the alternative way of using the volatile modifier to keep the register 102 00:19:16,330 --> 00:19:19,180 attached to the accumulator designs out with port?