1 00:00:01,190 --> 00:00:08,150 How can two hardware modules described in Atlas synchronize their communication, this lecture will 2 00:00:08,150 --> 00:00:12,650 explain the handshaking mechanism as a way of data exchange synchronization. 3 00:00:16,370 --> 00:00:23,030 Software functions communicate through their arguments in zero time, however, hardware modules which 4 00:00:23,030 --> 00:00:29,510 correspond to design top functions in Etchells communicate through ports with associated protocols, 5 00:00:30,230 --> 00:00:36,500 usually taking a couple of cycles to perform the desired data exchange and a simplified model. 6 00:00:36,620 --> 00:00:38,710 Hardware modules are connected. 7 00:00:38,840 --> 00:00:41,330 Why are a bunch of wires or signals? 8 00:00:41,930 --> 00:00:47,380 The values on these wires are valid at a specific time or during a time slot. 9 00:00:48,020 --> 00:00:55,610 Therefore, two modules can properly communicate if they are ready for exchanging data and are aware 10 00:00:55,610 --> 00:00:56,810 of these timings. 11 00:00:58,080 --> 00:01:04,800 This concept is usually called synchronization, in addition to timing, the number of wires is also 12 00:01:04,800 --> 00:01:08,790 important and two modules should also be aware of that. 13 00:01:14,330 --> 00:01:17,180 Hard for module use ports to communicate together. 14 00:01:18,270 --> 00:01:25,020 The number of signals and their characteristics are defined as the port interface, the associated protocol 15 00:01:25,020 --> 00:01:31,160 assigned to each interface defines the mechanism of data transaction and the corresponding port. 16 00:01:31,590 --> 00:01:37,860 In other words, a protocol defines the event sequences of the synchronization mechanism between two 17 00:01:37,860 --> 00:01:39,000 connected ports. 18 00:01:40,320 --> 00:01:45,540 The port interface and protocol concepts are very close and related. 19 00:01:45,690 --> 00:01:48,600 Therefore they are usually used interchangeably. 20 00:01:54,090 --> 00:02:00,900 As we know, the top function in a necklace is synthesized into a hardware module, also its arguments 21 00:02:00,900 --> 00:02:07,140 and return value are map to ports in the corresponding hardware module called by value a scalar. 22 00:02:07,140 --> 00:02:09,420 Arguments are assigned to input ports. 23 00:02:10,230 --> 00:02:11,700 Call Bio-Reference a scalar. 24 00:02:11,700 --> 00:02:14,880 Arguments are mapped to output or input ports. 25 00:02:15,480 --> 00:02:22,860 Arry and Pointer arguments can provide access to memories, so they need special attention in hardware. 26 00:02:23,250 --> 00:02:29,520 Although each argument is assigned to a port, the C C++ software language does not have any feature 27 00:02:29,520 --> 00:02:33,030 to define the interface and protocol assigned to each port. 28 00:02:33,420 --> 00:02:39,600 Therefore, the actual Astal should provide the mechanism to define interfaces and their corresponding 29 00:02:39,600 --> 00:02:40,290 protocols. 30 00:02:41,370 --> 00:02:47,520 The White Essentialists provides a complete list of industrial base interfaces to be assigned to design 31 00:02:47,520 --> 00:02:48,810 top function arguments. 32 00:02:49,260 --> 00:02:56,520 It also considers default interfaces for each argument based on the type of the design and access methods 33 00:02:56,610 --> 00:02:57,690 to the arguments. 34 00:03:04,250 --> 00:03:07,760 Modules on an FPGA usually uses the same clock signal. 35 00:03:07,880 --> 00:03:14,780 Therefore, the synchronization between them to generate and consume valid data is not so complicated. 36 00:03:15,840 --> 00:03:20,890 In simple cases, the shared clock can be used to synchronize a data transaction. 37 00:03:21,360 --> 00:03:28,020 In other cases, a few signals can be used to implement a type of handshaking protocol between two modules. 38 00:03:29,100 --> 00:03:35,940 However, when the hardware module inside an FPGA communicates with the peripheral, then synchronization 39 00:03:35,940 --> 00:03:40,080 between two modules is crucial and needs special attention. 40 00:03:44,550 --> 00:03:51,450 The communication among hardware in FPGA can be categorized into two groups, communication among modules 41 00:03:51,450 --> 00:03:59,790 inside the FPGA and communication between modules inside the FPGA and the peripherals outside each of 42 00:03:59,790 --> 00:04:04,230 these communications requires its own interfaces and protocols. 43 00:04:10,460 --> 00:04:16,730 What is the basic idea of communication protocol between two harder modules, the next lecture will 44 00:04:16,730 --> 00:04:17,610 answer this question. 45 00:04:21,490 --> 00:04:23,230 These are our takeaway messages. 46 00:04:24,480 --> 00:04:31,560 Two modules can properly communicate if they are ready for exchanging data and are aware of these timings. 47 00:04:33,070 --> 00:04:36,340 This concept is usually called synchronization. 48 00:04:37,500 --> 00:04:43,470 There are two data exchange groups among hardware modules in each of us, communication between modules 49 00:04:43,470 --> 00:04:50,690 inside an FPGA and communication between the modules inside an FPGA and the peripheral outside FPGA. 50 00:04:58,680 --> 00:05:05,160 Now, the quiz question give a couple of examples for data communication between a module inside an 51 00:05:05,160 --> 00:05:08,250 FPGA and a peripheral outside FPGA.