Index of /files/Udemy/Udemy - High-Level Synthesis for FPGA, Part 1-Combinational Circuits 2022-1/4. Basic Output/

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1. Introduction.mp4                                24-Nov-2020 00:00            63894145
1. Introduction.srt                                24-Nov-2020 00:00                4039
10. Vivado LAB.mp4                                 24-Nov-2020 00:03            84918363
10. Vivado LAB.srt                                 24-Nov-2020 00:03                9489
10.1 Basic-Output-Vivado-LAB-Quiz-Solution.pdf     24-Nov-2020 00:03              101502
11. Basis3 Board.mp4                               24-Nov-2020 00:03            70176802
11. Basis3 Board.srt                               24-Nov-2020 00:03                5299
11.1 Basic-Output-Basis3-Board-Quiz-Solution.pdf   24-Nov-2020 00:03              103595
12. Exercises.html                                 24-Nov-2020 00:59                1671
12.1 basic_output_exercise_02-vhls.zip             24-Nov-2020 00:03                1598
12.1 basic_output_exercise_03-vhls.zip             24-Nov-2020 00:59                1652
12.2 basic_output_exercise_02-vhls.zip             24-Nov-2020 00:59                1598
12.2 basic_output_exercise_03-vhls.zip             24-Nov-2020 00:03                1652
12.3 Basic-Output-Exercises-Solution.pdf           24-Nov-2020 00:03             1650077
12.3 basic_output_exercise_01-vhls.zip             24-Nov-2020 00:37                1624
12.4 Basic-Output-Exercises-Solution.pdf           24-Nov-2020 00:37             1650077
12.4 basic_output_exercise_01-vhls.zip             24-Nov-2020 00:03                1624
2. Output Configuration.mp4                        24-Nov-2020 00:00            48800596
2. Output Configuration.srt                        24-Nov-2020 00:00                3175
2.1 Basic-Output-Configuration-Quiz-Solution.pdf   24-Nov-2020 00:00              297702
3. Controller Concept.mp4                          24-Nov-2020 00:01            45695647
3. Controller Concept.srt                          24-Nov-2020 00:01                3065
3.1 Basic-Output-Controller-Concept-Quiz-Soluti..> 24-Nov-2020 00:01               82107
4. HLS Design Overview.mp4                         24-Nov-2020 00:01            53853363
4. HLS Design Overview.srt                         24-Nov-2020 00:01                3356
4.1 Basic-Output-HLS-Overview-Quiz-Solution.pdf    24-Nov-2020 00:01               82009
5. HLS Design Flow.mp4                             24-Nov-2020 00:01            97542525
5. HLS Design Flow.srt                             24-Nov-2020 00:01                7390
5.1 Basic-Output-HLS-Designflow-Quiz-Solution.pdf  24-Nov-2020 00:01              205516
6. HLS CC++ Design.mp4                             24-Nov-2020 00:02            75974410
6. HLS CC++ Design.srt                             24-Nov-2020 00:02                5168
6.1 Basic-Output-HLS-CC^M^MDesign-Quiz-Solution..> 24-Nov-2020 00:02              124832
7. HLS Ports.mp4                                   24-Nov-2020 00:02            64365185
7. HLS Ports.srt                                   24-Nov-2020 00:02                4526
7.1 Basic-Output-HLS-Ports-Quiz-Solution.pdf       24-Nov-2020 00:02              123271
8. HLS LAB.mp4                                     24-Nov-2020 00:02            89571968
8. HLS LAB.srt                                     24-Nov-2020 00:02               10841
8.1 Basic-Output-HLS-LAB-Quiz-Solution.pdf         24-Nov-2020 00:02              255569
9. Vivado.mp4                                      24-Nov-2020 00:03            84071625
9. Vivado.srt                                      24-Nov-2020 00:03                5641
9.1 Basic-Output-Vivado-Quiz-Solution.pdf          24-Nov-2020 00:03               80337