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How to use the Xilinx Vivado to generate the FPGA bitstream? The generated RTL IP by the Vivado-HLS 
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toolset requires the logic synthesis process to be converted to an FPGA bitstream. 
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The Xilinx Vivado Suite 
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can do this process.
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In this video, I am going to use this tool to create the FPGA bitstream file.
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Now run the Vivado IDE which can be done by double-clicking on the related icon on your desktop 
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or clicking on the program link in the "Start Menu" in Windows OS. If you are using a Linux based system, 
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you can run vivado command for this purpose.
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After running the Vivado, the first page appears where you can start managing your project.
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On the Quick Start section, you can create a new project or open an existing project. 
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There is also a list of the recent projects on the right-hand side that you can choose from and continue 
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working on your previous projects.
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Let's create a new project by clicking on the "Create Project" link. Then the "create new project" wizard 
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starts.  Press Next.
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Select a name for your project and set a destination path for that. 
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It is a good practice to select the "Create project subdirectory" option. 
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Click next to get to the next step.
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Choose RTL project, as we don't have any source file in this course select "Do not specify source 
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at this time" option. And click Next. Choose the target FPGA or Board. Click on the board, choose digilentinc.com 
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from the vendor list and then select the Basys3 Board and press 
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Next, After reviewing the project summary, press on the Finish button to create the project. As we are 
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going to use the IP generated by Vivado-HLS and probably some of the IPs from the Xilinx library 
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and we don't have any RTL source file, so we follow the Xilinx IP integrator design flow.
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This design flow starts with creating a block design. For this purpose, click on the "Create Block Design" 
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link on the left hand-side pane.
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You can choose a new name for the design or keep the default.  
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Let's keep the default. The Diagram 
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window appears to draw our design.
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First, we make our generated IP by Vivado-HLS accessible for the 
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Vivado IP integrator.
For this purpose,
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right-click 
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anywhere on the Diagram area and choose "IP settings…" from the drop-down menu.
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The setting window appears. Select IP->Repository from the left-hand side 
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list of options. In the IP Repository section on the right-hand side,
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click on the plus icon.
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Find the Vivado-HLS directory that you have already created for the basic_output project. 
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If you have multiple solution folders under the Vivado-HLS project directory, choose the desired 
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one and press Select. Viviado searches the solution folder for any possible IP available and adds the folder 
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to its repository. Click OK in the Add Repository dialog box.
Then press OK to get back to the Vivado IDE.
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Now press the plus singe in the middle of the Diagram area or right-click anywhere on the area and select 
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Add IP from the drop-down menu. In the search field, 
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write the name of your IP, which is basic_output in this lab.
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Double click on the IP name to add that to our design.
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Our IP with one output port appears in the Diagram area.
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Select the port and then right-click and select “make external” option. 
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You can change the name of the port and give that a more convenient name. 
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As this port drives the LEDs, we change the name in the external port properties view to led. Notice that 
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this port is a vector of 8 signals. 
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Then the individual signals can be addressed by led[0] to led[7]. To connect the design external-
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port to the FPGA pins that are connected to the LEDs on the board, 
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we should create a constraint file to define a set of physical I/O pin constraints.
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For this purpose, click on the Source tab on the left-hand side of the diagram area. Then right-
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click on the Constraints folder and select "Add Sources …" option.
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In the add sources dialog, make sure that "Add or create constraints" is selected then press Next button.
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and then click on the "Create File" button.
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Here you can choose a file name in the dialog box. For example, basic_output then 
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click OK and Finish.
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The XDC file editor will be opened to add your constraints.
Instead of adding constraints from scratch, you can use 
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the related XDC file provided by the board vendor and uncomment and modify the required constraints.
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Connect to digilent gitub site at https://github.com/Digilent/Basys3 
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then go the Resources/XDC path, open the Basys3_Master.xdc file and copy all its 
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contents into the xdc file in your  vivado project. To connect our design output to 8 LEDs, 
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we uncomment the first 8 LEDs constraints in the LEDs section. 
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The signal name in the constraints is LED, which is exactly the same name as the external port in 
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our design.
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So, no other changes are required.
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Right-click on the design name in the Sources tab and click on the "generate output products…" option. 
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This process creates some internal files and structures required for the rest of the Vivado design flow.
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The Generate Output Products 
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dialog will be opened. Accept the default values and click on Generate button.
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Then right-click on the design name in the Sources tab again and select the "Create HDL Wrapper…"  option,
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which creates an HDL top file that encompasses our design .
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Now we are ready to generate the FPGA bitstream.
ON the left-hand side pane, click on Generate Bitstream 
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under the PROGRAM AND DEBUG section.
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It takes a couple of minutes to generate the FPGA bitstream.
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After generating the FPGA bitstream, we are ready to program our FPGA board. In the next lecture, 
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I will explain that.
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These are our takeaway messages.  To be able to use the IP generated by Viviado-HLS in the Vivado IDE, 
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we should add that to the IP repository.
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The list of constraints provided by the Basys3 board vendor can be used and modified to add 
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constraints to our design targeting this board.
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Now, the quiz question. Keep the default port name in the design, then modify the required constraints 
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and generate the FPGA bitstream.