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Having a big picture of the HLS design flow can help us to design a logic circuit with confidence.  
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So, here I'm going to explain the HLS design flow briefly.
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More details will be described along the course.
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The complete HLS design flow consists of three steps: Step 1- Describing the design and performing 
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the high-level synthesis using Vivado-HLS toolset. Step 2- Running the logic synthesis and
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applying the I/O pin physical constraints using Vivado toolset. Step 3- Configuring the board and verifying 
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the output results. In the vivado-HLS step, 
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we can do the following tasks that some of them are optional: Coding Functionality in C/C++,  Inserting
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port Interface directives,  Inserting optimization directives, 
C-Simulation,  Debugging,  Co-Simulation, 
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and IP generation.
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In this lecture, we only perform the three tasks in red which are Coding functionality in C/C++, Inserting 
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port interfaces and IP generation. The logic synthesis generally consists of these tasks:
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Integrating the generated HLS IP into Vivado design space, Adding Constraints,  Synthesis,  Implementation, 
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and Bitstream Generation.
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In the last step, we configure the board with the generated bitstream.  
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This step generally consists of three tasks: Program the board, Provide the inputs, Investigate
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the outputs. As our design is simple and doesn't need any input, 
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we only check the outputs.
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The next lecture gives more details about the design-flow in Vivado-HLS. 
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I will explain that the design-flow has six steps, some of which are optional. 
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The takeaway message from this video is that an HSL design flow consists of three steps:
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The first step in using the Xilinx Vivado-HLS to describe the design in C and synthesis that
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into the corresponding HDL code and IP.
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The second step is integrating the generated IP and the required constraint files into Vivado toolset 
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and performing the logic synthesis.
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The last step is generating the bitstream and program the board and examine the design.
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Now the quiz question. Which two tasks can be performed in Vivado-HLS:
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1- Bitstream generation
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2- Adding physical constraints 3- Co-simulation 4- Debugging 5- Logic Synthesis