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Now that we know the LED board configuration as one of the board output mechanisms, we should be 
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able to describe a simple logic circuit in HLS for driving these LEDs. In the following slides,
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I’m going to talk about the concept of the structure of this driver.
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This picture shows the Basys3 board, which contains an FPGA and 16 LEDs and the connections between 
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LEDs and some of the FPGA pins. Our goal is to design a simple logic circuit to derive the corresponding pins 
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with the proper data to turn ON/OFF LEDs. 
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To control the illumination of an LED, the design, inside the FPGA, should send the logic value 
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“1” or “0” to the corresponding pin.
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The design that generates these “1”s and “0”s would be a C function. This design is inside the FPGA and 
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is not connected to the FPGA pins.
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Therefore, we need another part that represents the connections between the design outputs and the FPGA 
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pins.
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These connections cannot be defined inside the C function and should be denoted in a separate file 
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by using some instructions that are known as physical constraints. 
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I will explain the constrains later in this section. Now, after being familiar with the board and having 
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a big picture of our design, 
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The question is how we can start implementing the functional blocks and their corresponding connections.
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For this purpose, we should know more details about the design flow and the tools suitable for implementing 
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each part of a design.
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The takeaway from this video is that an FPGA design controlling a peripheral has two main parts: A functional 
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block inside the FPGA that can be described by HLS techniques. And the connections between the functional 
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block ports and FPGA pins. Notice that both these parts are located inside the FPGA.
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Now the quiz question. Which part can be implemented with an HLS C/C++ function? 1.	The logic circuit 
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functionality inside the FPGA2. Connections between the logic circuit inside the FPGA and the FPGA pins 3. Connections 
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between the FPGA pins and the LEDs on the board