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How can we convert a hardware IP generated by Vivado-HLS into the FPGA bitstream? In order to generate 
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generate the FPGA bitstream file, the Xilinx Vivado toolset should be used.  In this lecture, 
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I am going to explain the basic steps of how to use Vivado toolset to generate the final FPGA bitstream.
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After having the hardware IP, we can import that to the Vivado design suite. Our IP only has an output 
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port which is an array of 8 binary signals. As shown in this slide,
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I’ve changed the name of the port to led as they will be connected to LEDs on the board. 
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The led[7:0] 
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array represents the eight connection signals inside the FPGA. 
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But, what should we do to connect these internal signals into the FPGA pins connected to the LEDs on 
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the board?
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We need eight connections to connect design output ports into U16, E19, U19, V19, W18, U15, U14 and 
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V14 FPGA pins.
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This is the place that the concept of physical constraints comes into play.
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Design constraints define the requirements that must be met by the compilation flow in order to make 
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the hardware design functional on the board. 
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As we know, a typical FPGA has several I/O pins to communicate with external modules. A 2D coordinate 
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index indicates each pin location. As part of the FPGA reconfigurability, 
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these pins can provide different voltage levels and electronic signalling based on the standard assigned 
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to each pin by the designers.
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For example, based on a specific I/O standard, a pin can provide 3.3v, 2.5V, 
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or 1.8v for the high logic value or deliver a different level of current 
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to drive external devices. 
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Also, a single-ended or differential I/O standard can be assigned to an FPGA pin.  For example, 
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LVCMOS33 is a 3.3 volt, Low Voltage CMOS and single-ended I/O standard. To connect 
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each design port to
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an FPGA pin, two properties should be defined: pin location and standard. The I/O constraints can determine 
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the location and standard of each FPGA I/O pin connected to a port in a design. 
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The Xilinx Viviado toolset uses the TCL language to describe an I/O constraint.  This constraint command 
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has four fields:
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set_property keyword <property>, <value>, and <object list>
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For example, for the first connection in our simple LED controller, two constraints should be defined 
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using this format. The location and I/O standard.
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Usually, board vendors provide a list of all FPGA I/O constraints in a file with .xdc extension that 
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can be used by designers.
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The BASYS3 board also has such a file called Basys-3-Master.xdc that can be found on its 
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vendor GitHub site. 
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This file contains the constraints for switches, leds, 7-segments and other hardware connected 
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to the FPGA.
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Note, in the original files all constraints are commented by #. 
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All the constraints defined for the lower 8 LEDs are shown in this slide that can be used after
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uncommenting the desired constraints and change the object names. 
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Here, all required constraints are uncommented. As we used the led as the port name, the object names 
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have been remained unchanged.
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Now that we know the basic concept of integrating an IP into the Vivado Suite toolset, We should practically 
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use the Xilinx Vivado to generate the FPGA bitstream for our LED controller design.
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The next lecture will explain this process.
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These are the takeaway messages. To connect the IP ports into the FPGA pins, 
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we should define some constraints.
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The main constraints determine the pin location and pin electrical standard. 
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Now the quiz, question. How many constraints in total should be added to our design in Vivado toolset?