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In this video, I will show you how to use the Xilinx Vivado–HLS toolset to implement the simple
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LED controller explained in the previous lectures.
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Here, I'll walk you through the basic steps of developing a hardware design with Vivado-HLS.
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Therefore, by the end of this lecture, you will practically learn how to use Vivado-HLS to describe 
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a hardware module in C/C++.
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These are the steps that we are going to follow
In Vivado-HLS, we Create a project,  Add a source file, Perform 
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High-Level Synthesis, Generate IP.
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Let's get started. First, run the Vivado-HLS IDE which can be done by double-clicking on the related 
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icon on your desktop or click on the program link in the "Start Menu" in Windows OS. 
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If you are using a Linux based system, run vivado_hls command to start the Vivado-HLS IDE.
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After starting the Vivado-HLS, it shows you the welcome screen where you can see the options to create 
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or open a project. If you don't see the welcome screen for any possible reason, you can open that
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by going to Help menu and select the Welcome… option.
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You can also find your previous projects in the "Resent Projects" area. 
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If this is the first time you run the vivado-hls, the welcome
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screen doesn't show this part.
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A few links to the related documents are also shown in the welcome screen.
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Here, we start by creating a new project. For this purpose, 
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click on the "Create a New Project" icon. Then the create new project wizard starts. The first step
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asks you to choose a name for the project and modify the project location.
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The name of the project will also be the name of the folder that contains the entire project files.
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The next step asks you to add design files if they already exist.
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This page also asks you the name of the "top function" which would be the name of the hardware module
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entry function. 
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Notice that each hardware module can only have one top function.
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All other functions in the design should be called through this top function using a possible hierarchy 
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of function calls.
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If you don't know the top-function name or you haven't prepared the design files, just click next, as 
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we can define that later.
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The next step asks you to add the testbench files. 
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As for the sake of simplicity we don’t have the testbench file in this first lab, click next to get to 
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the "Solution Configuration" page. 
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In this page, you can configure the design clock and define the target FPGA. 
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Here you can choose a solution name which would be the name of the subfolder inside the project folder 
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that keeps all the files generated by the HLS flow.
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As we only consider the combinational circuits in this section of the course, you can ignore the 
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clock-related parameters in this page.
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Choosing the target FPGA is necessary. 
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Click on the ellipsis icon. 
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Here you can select a specific FPGA or a particular board. 
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Click on the board, from the vendor menu, choose the digilentinc.com and find the Basys3 in 
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the list of boards. Pressing the Finish button opens 
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the Vivado-HLS graphical User interface or GUI. The Vivado-HLS GUI consists of four panes 
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as default.
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We will explain them as we use them.
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We start with the project explorer view on the left. 
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If you cannot see this pane, go to Window menu and select 
Window->Show View->Explorer
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In the Explorer view, 
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you can see the list of objects associated with our project. 
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It contains, the default included hearer files, 
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source folder which is empty at this point, Test bench folder which is also empty, and the Solution
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directory Which only contains the constraints files at this step. We'll explain that later. To add a design 
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file
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right 
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click on the source folder and select the "New file …" option. Choose a file name, for example, "basic_output.cpp"
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And press the Save button.
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A proper editor opens the file which is empty at this stage.
Start and add the basic_output C function. The
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function has an output argument, so it should be defined as a pointer. 
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We are using the 8-bit unsigned char as its data type. 
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The function body has just one line which put the constant binary value of 11110000 
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to the output argument.
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Now, we should add HLS pragmas for the output port and function block.
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There are two ways to add pragmas to the code
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The first is adding manually to the source code
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The second approach is using the Directive view on the right-hand side pane.
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If you cannot see this View, select Window->Show View->Directives from the menu bar.
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There are two groups of pragmas.  The top-level function pragma which adds some control signals to the 
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synthesised hardware
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And the port-related pragmas. As our design is a simple combinational circuit, these two groups 
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of pragmas do not define a specific interface. To add the function level pragma, right-click 
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on the function name in the Directive View. 
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Then select "Insert Directive" from the drop-down menu. 
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Then select the INTERFACE directive. In the options part, choose ap_ctrl_none as the mode.Choose
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the source file in the destination section. Then press the OK button. A new pragma should be added to 
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the source file under the function definition. Then right-click 
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on the argument name in the Directive view and select the "Insert Directive…" option.
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Then select the INTERFACE directive, 
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In the options part, choose ap_none as the mode. Make sure that the "Source File" is selected as the Destination.
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Then press the OK button. Another pragma should be added to the source file.
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Now you can save the file.
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After saving the file, we are ready for performing the synthesis. Click on the synthesis icon.
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You can follow the report messages in the Console view in the lower pane. 
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It takes a couple of seconds to finish.
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At the end of the synthesis report, you can see a summary of the hardware interfaces which should 
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contain only one port with ap_none protocol. After synthesis, we can wrap up our design into a package 
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by pressing on the "Export RTL" icon on the toolbar. 
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The Export RTL page is opened. 
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Accept the default values and click on the OK button.
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The RTL package or IP will be generated after a couple of seconds.
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Now we are ready to use this IP in the Vivado IDE to generate the final bitstream.
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Now that we have transformed our HLS design into an RTL IP, the question is
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How can we integrate the IP into the final design to program our target FPGA? The next lecture will
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cope with this question.
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The takeaway message from this lecture is
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Main tasks for developing a design in Vivado-HLS are Creating a project, Writing the design functionality 
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in C/C++, Synthesising the design,  Generating the corresponding RTL IP.
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Now the quiz question
Use the following C function as the LED controller that returns the LED values, 
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then generate the corresponding IP using the Vivado-HLS.