0
1
00:00:00,860 --> 00:00:07,070
The next step after generating the FPGA bitstream file is to download it into the target FPGA device.
1

2
00:00:07,460 --> 00:00:13,760
The Vivado IDE tool includes functionality that allows us to connect to hardware containing one or 
2

3
00:00:13,760 --> 00:00:19,320
more FPGA devices to program and interact with those FPGA devices. In this lecture, 
3

4
00:00:19,460 --> 00:00:22,490
we are going to walk through the FPGA programming process.
4

5
00:00:24,330 --> 00:00:31,260
Conceptually, an FPGA comprises of two layers: application and configuration layers. The application 
5

6
00:00:31,260 --> 00:00:36,450
layer contains all the hardware modules that can be configured and connected together to implement an 
6

7
00:00:36,450 --> 00:00:37,650
algorithm or a function. 
7

8
00:00:38,370 --> 00:00:43,680
After configuring this layer, we can apply the input data and get the generated outputs. 
8

9
00:00:43,980 --> 00:00:49,350
The configuration later consists of a set of memory cells used to configure the application layer modules. 
9

10
00:00:50,070 --> 00:00:56,040
The configuration data saved in this layer is call bitstream and is generated by synthesis tools. 
10

11
00:00:58,540 --> 00:01:04,870
Theoretically, the configuration memories are accessible sequentially, and FPGA bitstream data is written 
11

12
00:01:04,870 --> 00:01:06,700
to the FPGA using a streaming scheme. 
12

13
00:01:09,090 --> 00:01:14,640
There are five steps to configure our board with the generated bitstream file. Firstly, connect the board to the 
13

14
00:01:14,640 --> 00:01:16,450
computer with a micro-USB cable.
14

15
00:01:16,770 --> 00:01:21,540
Secondly, If your project is not open, run the Vivado IDE and open the project.
15

16
00:01:21,560 --> 00:01:27,360
Thirdly, Open the Hardware Manager which controls and manages all the connections and data communication 
16

17
00:01:27,540 --> 00:01:32,190
with the target hardware. Then, open the target FPGA, using a hardware server. 
17

18
00:01:32,400 --> 00:01:37,530
The hardware server creates a connection from the Vivado Design Suite to the physical programming
18

19
00:01:37,530 --> 00:01:37,950
target.
19

20
00:01:37,980 --> 00:01:41,650
Before programming the target FPGA, you should attach the bitstream file.
20

21
00:01:42,000 --> 00:01:43,920
Finally, program the FPGA.
21

22
00:01:46,030 --> 00:01:52,480
Ok, let’s do these steps in practice. First, connect your board to your computer. If your project 
22

23
00:01:52,480 --> 00:01:55,180
is not open, run the Vivado and open your project.
23

24
00:01:56,530 --> 00:02:01,900
Probably you can find your project in the resent project area on the right, or you can click on Open 
24

25
00:02:01,900 --> 00:02:06,400
Project in the QuickStart section, or use the menu for this purpose. 
25

26
00:02:07,270 --> 00:02:12,850
In the case of using one of the last two options, the open project dialog will be opened, find your 
26

27
00:02:12,850 --> 00:02:14,110
project and select that. 
27

28
00:02:14,380 --> 00:02:18,400
Notice that the extension of the Vivado project file is xpr.
28

29
00:02:19,000 --> 00:02:24,460
Click the Open Hardware Manager link in the Program and Debug section of the Vivado flow navigator.
29

30
00:02:25,060 --> 00:02:31,360
Click the Open Target selection under Hardware Manager in the Program and Debug section of the Vivado flow 
30

31
00:02:31,360 --> 00:02:35,140
navigator and select the auto-connect to open the hardware targets.
31

32
00:02:35,620 --> 00:02:38,320
You should see the FPGA device in the list of hardware. 
32

33
00:02:52,270 --> 00:02:57,790
Now program your device. You have two options for doing that 1- Right-click on the name of FPGA 
33

34
00:02:57,790 --> 00:03:03,850
and select the “Program device …” option. 2- Or click on the Program device link on top of the hardware pane
34

35
00:03:10,080 --> 00:03:16,260
The program device dialog will be opened. If your bitstream file is not denoted in the Bitstream file box,
35

36
00:03:16,530 --> 00:03:22,590
click on the ellipsis icon and find the bitstream file and select that. Then click on the program button. 
36

37
00:03:22,590 --> 00:03:26,810
After programming the board, you should see 4 LEDs illuminating. 
37

38
00:03:34,100 --> 00:03:39,050
In the next step, you will have a couple of exercises to master what you have learned during this 
38

39
00:03:39,050 --> 00:03:39,410
section.
39

40
00:03:42,380 --> 00:03:43,670
This is our takeaway message.
40

41
00:03:44,030 --> 00:03:47,800
There are five steps to configure our board with the generated bitstream file.
41

42
00:03:48,410 --> 00:03:50,600
Firstly, connect the board to the computer
42

43
00:03:51,380 --> 00:03:53,610
Secondly, open, the Vivado project  
43

44
00:03:54,560 --> 00:04:02,600
Thirdly, Open the Hardware Manager, Then, open the target FPGA, Finally, program the FPGA.
44

45
00:04:05,010 --> 00:04:08,820
Now the quiz question. What are the hardware manager and server?