Index of /files/Udemy/Udemy - Learn VHDL and FPGA Development 2018-8/13. Lab 3 - Universal Shift Register/

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1. Introduction.mp4                                05-Sep-2018 02:00             5312143
1. Introduction.srt                                05-Sep-2018 01:56                2210
1. Introduction.vtt                                05-Sep-2018 01:56                1950
1.1 Sim_Mem_Init.zip.zip                           05-Sep-2018 01:56               24184
1.2 Lab-3.zip.zip                                  05-Sep-2018 01:56               62981
2. BASYS 3 Universal Shift Register Demonstrati..> 05-Sep-2018 02:05            74064090
2. BASYS 3 Universal Shift Register Demonstrati..> 05-Sep-2018 01:56                4790
2. BASYS 3 Universal Shift Register Demonstrati..> 05-Sep-2018 01:56                4218
3. BASYS 2 Universal Shift Register Demonstrati..> 05-Sep-2018 02:06            65331109
3. BASYS 2 Universal Shift Register Demonstrati..> 05-Sep-2018 01:56                8378
3. BASYS 2 Universal Shift Register Demonstrati..> 05-Sep-2018 01:56                7338
4. BASYS 2 Universal Shift Register Solution.mp4   05-Sep-2018 02:05            73029251
4. BASYS 2 Universal Shift Register Solution.srt   05-Sep-2018 01:56               28410
4. BASYS 2 Universal Shift Register Solution.vtt   05-Sep-2018 01:56               24700
5. Universal Shift Register VHDL Design.html       05-Sep-2018 01:56                2150