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Go Welcome to the fab three solutions video in this video one will walk you through the steps needed

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to complete lab 3.

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So in the lab 3 section there is a zip file lab three which you go ahead and download and unzip which

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I've done here on a desktop.

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Then when you zip that there you will see there are there is a folder called tests a score bench on

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a score Ellaby.

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This is contains a home a library package it'll be used in your test bench.

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Don't worry about it.

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However make sure you don't delete it otherwise your testbench will simulate.

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So just leave that folder go in and make sure you keep the structure the same that's very important.

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As far as the DCL script I give you know we've got this U.S. Our folder which if you go and open that

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up that's what contains your VH DL file.

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The US are the HD filer here and TACL script your test bench your test us are an input output which

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are CXXVI files.

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These were your testbench uses and you get your lab 3 tasks which will open up here.

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And as you can see we've got four different tasks here for lap three tasks one is to complete the U.S.

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HD file by filling in question marks and then we want to create a Mollison project using module 7.1

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as a reference to successfully simulate your just your design.

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Then after we successfully simulate it model Sam will want to create a project in Xilinx C and to create

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a file that will use that file to load onto the FPGA and verify that everything's working as expected.

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All right.

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So for the first task is to simulate or fix essentially the the US or file the VHDL file.

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So what I want to do is go ahead and.

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OK I'll go into this us our folder here in your lab three directory and go ahead and open that up I'm

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going to do these edits with notepad plus plus.

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You can do them with any editor really you could even use just regular notepad.

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However I like Notepad plus plus because you can select your language to VHDL and there it picks up

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on that and explain syntax and gives you a different color so you can kind of note between keywords

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and comments and everything else.

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So here's our US our VHDL file.

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So I'll give you the task by label and here in the file and some comments and then go to our libraries

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or entity.

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And if you go through you'll see I've got this a sequel to this question mark.

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Well these are basically you've got to go through and figure out what these are.

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So first thing to do is we're going to go ahead and open up models because this is typically the the

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process I'll go through in order to solve this.

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So we open up model Sam we've got to file new.

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Are we going to file change directory and we want to navigate to that U.S. our directory which is in

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the fab 3 folder us our.

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I click OK and yes see your transcript window kind of telling you what's going on and to file new library

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because anytime you create a change your directory in your work with models you have to have a library.

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This is where it stores the simulations and everything.

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You only have to do this once if you open this directory up later on.

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And it's you still have the library called work which I'll show you here once.

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So you just want to select a new library and a logical mapping to it.

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And the default is work which is fine that's just what I leave my house.

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Go ahead click OK.

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And if we open up go to this directory here you'll see we've got this lab three US are.

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We've got this Madison configuration settings file and it creates this work folder which we go into

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there.

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There's just that's where when we simulate it's going to store all that data in there.

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So that's all that's really doing.

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All right.

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So now we're going to go ahead and we're going to attempt to simulate this.

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So I'll go to my tools TCO execute macro and you want to select that you start PCL file that is included

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in your lab lab 3 former structures.

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Go ahead and select that and it's going to tell you which this is where you get the transcript down

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here.

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It's saying it's got some errors.

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And this is where it's telling you and then your USRA HD file line 47 and there is a syntax error.

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And so if you go into here line 47 had picked it up.

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It does not recognize what that question mark is and because questionmark is not is not defined basically

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so.

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And that's why I did that.

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They are designed to make you go through and hopefully figure all this out.

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So ok for this line 47 it's telling us we need to sign the output to what.

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Well if you look here.

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We're going to sign that to a wretch because we can't read what the value of a is.

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And so we're going to have this signal a ridge that we modify and associate it with this output.

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So to solve that we'll go ahead and type in the range and as you'll see it will pull up a little box

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saying all they read is that what you want to use and yes we do hit enter and so no that that should

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be fixed so let's go ahead and go to the transfer window a model sim right click clear.

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That clears it out and we'll go Hago tools DCL execute macro while we execute it and see we still got

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more errors.

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But exactly that was a problem I didn't save it.

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So you had to go through here and it still picked up on the error on line 47 because we didn't say this

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so it hit save.

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We'll go for it I get it real quick I'll clear that.

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Go to Tools to C-L execute macro or us are TCO.

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And now it's saying we've got an error on line 53 and got 69 75.

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However typically this isn't all the errors like Usually after picks up one or two errors it'll just

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exit because at that point it doesn't know what's going on so you open this up and we'll go to line

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53 that's for the next areas right here.

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It doesn't recognize that questionmark again.

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So we've got to go through this.

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And so far I hear basically this is a VHDL process and we want this to be evaluated on every clock cycle.

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So what do we need to put insensitively less we need to put the clock signal and the sensitivity list

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which appear in our entity declaration is our clock has to find us.

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OK.

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So if I go ahead and put C OK in there and then I want to save and I'll run through this one more time.

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Clear your transcript models then go to Tools TCO execute macro select the TC file again open and now

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it's telling us on line 58 and basically outhe's continue this process until eventually a model some

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will go ahead or compile everything when all of the errors are gone.

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All these question marks in and you see a note saying that you successfully simulated the US are so

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we're going to go ahead and just go through I just did the first C like that just to kind of create

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the process I usually go through.

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So as we go down here to line 58 we're in a reset process so on every clock edge we're checking to see

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if the reset is one or if it's being pressed and if it is being pressed we want to set a red edge to

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zero because every edge is tied to AA which is our output.

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So if I go ahead I'll just put a zero in there.

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That should fix that air will save more to keep on moving down and then we'll attempt to see if we if

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we got this right.

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So now this case statement is evaluating the signal s which appear on our input.

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Here is a standard logic vector one down at zero.

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That's two bits and representative.

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If it's a 0 0 with both bits are low we want to hold.

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Well for one to whole we want every edge to be a red again.

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So where just put a edge there that hopefully should solve that air.

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Now we have this whole right shift process.

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This is where we got to 0 1.

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We want to shift everything to the right and so we're shifting everything to the right.

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If you think about it the the far left most bit is going to be the state or with which we have set as

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a minus one which is a 7 a ridge on a 7 is the MSP most significant bit.

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We want that to be zero.

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Because you are shifting over we're basically filling in zeros.

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So in order to make that zero 0 0 there.

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Now note I have to put if I follow up I would just leave this like that as a zero.

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This would give me an error which I'll go ahead and show you here.

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We'll save here.

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Clear tools.

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Just yell execute macro.

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Us are open that up and line 66 is tell us we got there and that's right here.

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That's because I need to put those apostrophes on your side of it as you can see here down on line 73.

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There's.

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I've got those apostrophes on it.

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And that's because the standard logic vector.

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If this was an integer that would be OK.

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So I've got to put these different apostrophes in there and that.

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Now that should except that if I clear tools to execute macro

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and that's and that's the process this is a process I want you to use and you go through here.

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So now it's time we've got to err on line 69 which we know because we haven't figured this out.

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So now we need to determine OK we're in the right shift process so we went and we took our leftmost

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bit made that a zero.

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Now we need to make the rest of them equal to what the previous ones were before and basically just

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shifted over and essentially you can just use his left shift process as a as a reference.

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So over here we're going to want to make this equal to a ridge or dedo.

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That's our generic minus one down to one and then therefore basically we're taking all this data with

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two here and we're doing our right shift with it.

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So save that and then we've got on this line 75 here a serial load.

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OK.

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So you want to load.

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This is where we load values in.

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So we're going to loaded it on a registry and we determine what what value do we want to load in.

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Well what's our input entity value our input into the value.

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Is this I instead logic school for make that and I go ahead and save now see let's try and simulate

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this.

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OK.

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Tools you know execute macro.

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Open that up and OK everything compiled successfully and voila.

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You see we get this note.

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No success us our test completed.

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So I'll go ahead right click zoom fool.

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You can see all all the way form everything that's going on here which is a little bit difficult to

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read.

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You can sit here and go through all these toggling a clock cycles and making sure that all your bits

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are shifting as as expected.

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But when you get the more complex designs this really is not not what you want to be doing.

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So typically it does have as you get more advanced you'll learn how to write test benches and inside

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a test bench if everything works as expected you'll get this note saying success.

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And usually in design process you have a separate engineer who will create the test bench.

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That's compared to you and then that way if if his test bench successfully completes your design then

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you say that your design is verified and ready to go.

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So all right.

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So we've got that we've got the first two steps completed.

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We went ahead and we completed the lab we successfully all the question marks in our code.

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We went through and got it to compile successfully and we were able to successfully simulate and model

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them.

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And that's usually the flow you're going to want to use with all the rest of.

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Right here you're going to probably end up.

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And that's why I give you this DCL scripts you're going to be having an editor like Notepad or whatever

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you're using to edit these files and you're going to edit them save your tools TCO.

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Run a macro run the macro script and just keep reading the transcript they're just going to tell you

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the line where your errors are at and just keep following that until you get to successfully simulate

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this.

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So all right our next step is we want to go ahead and create a project in ISC.

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So go ahead.

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All right so now that we've completed our model sim simulation we want to go ahead and create our Xilinx

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science project.

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So go ahead and bring up the IAC and you'll see the screen here.

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We're going to go ahead and click on the new project and we want to go ahead and navigate to another

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location.

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Navigate to our lab three and click on the US are opened up and then give with the name we just want

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to want to make it.

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USRA because that's the same name as the entity which is just good practice to do so.

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Click next and you want to select all the project settings that are tied to the FPGA you're targeting

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which were targeting a Spartan 3 on the basis to board which is the device ex-chief 3 x 100 the package

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C.P. 1 3 2 SPI dash 4.

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If you're using any other type of development board you'll find all this information located in the

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User Guide or even if you look at the board itself.

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The FPGA chapel typically have to have a part number on there you can look that up online and figure

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all this information for here.

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Most of the stuff once you select these first five different values the rest is here you can pretty

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much leave as as our state are so good.

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Next gives your project summary finish.

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And here we've got an empty project.

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The US are going to go ahead and select the project add source and got to go back one level to find

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this US R-FL.

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Now since we went ahead and successfully simulated this a model said there should be no problems with

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this workings.

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Why not go ahead and add the source file.

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If I double click it give me.

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You'll note it should have picked up all the different as you can see we've got a ridge there picked

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up all the different changes we made on it there.

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So if we had not made those changes and mouse them and we try to synthesize this it would give you errors

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and you could debug down here.

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However you could have it wouldn't stick.

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It might not necessarily work well it's going to do is tell you this.

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Syntactically it's correct.

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It just it may not be doing what you want it to do.

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Like we could tie this a two we can make it it had a second signal one here and tie it to that and change

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it or.

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The biggest problem would be in this right shift left shift.

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We could mess that up.

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We could say OK instead of data register with minus one and make it data register with minus 2 and so

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on and so forth then we could have something that works be thrown on the board it doesn't do what you

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want.

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So OK so now we need to add the U.S. file to a project source and then all us our.

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So here you go up to the lab three the top level you've got that this U.S. file.

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I want to go ahead and select Open on that.

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OK.

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And now you expand this down and you want to make sure that your the HD files are top level which has

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this three triangle type of thing going on with double click or you see efile you can see we've got

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now in our beach do you we've got a which is a standard logic vector data with one minus one down to

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zero in our data with a.

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So it's a standard logic vector 7 down to zero which if we go all you use in order to associate each

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one of those values we've got a zero through a seven.

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So we're tying a zero to location 5 which like in the User Guide and 5 is a good output to an LCD on

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the basics to board.

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And all right so now we've got all the files we need in here.

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So we got to select our U.S. our behavior VHDL file.

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You'll notice if I select this us our ECF file it doesn't give you options to generate a bit file because

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you can't generate it with just that you need a VHDL file.

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So we select that and it gives us all these options down here we can do.

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So we want to go to implement design right click run and I'll tell you it's running self-assess it's

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going through and synthesizing and checking and syntactically making sure that everything is correct

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which if you got to simulate correctly in Madison this should be working no problem.

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You may get a few warnings telling you that your software subscription period has lapsed.

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However if you just recently download the probably won't see this warning.

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I've I've had the software on my computer for several years so that's why it's giving me a warning but

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it's nothing nothing major If you see that don't worry about it.

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Then the next thing one is generates the programming file.

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Go ahead and click run.

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And this is going to create our top file which is the actual file We're going to load onto the FPGA.

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So once you create and that's a staggering check saying that that's that's good.

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Once you create this file you can literally take this file anywhere.

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You can e-mail it to someone and they can load onto their FPGA because that contains everything it ties

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in this VHDL file.

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This design turns it all into the logic gates that it synthesizes to and this file and ties all these

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inputs and outputs to physical pins located on the FPGA.

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And that's that's that's the thing we want we want that program file.

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So that's generated.

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We can go ahead and minimize that number want to open up a dept before you do that.

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Make sure that on your bases to board your jumper 3 is there is PC and Rom make your on PC.

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This does you need this to be connected otherwise your computer won't recognize the board and you will

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bear load any files on it.

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So make sure selected the PC power on and plug it into your computer.

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Open up it dept and you should see something similar to this now.

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Right now it says no device is identified.

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So go ahead and click initialized chain and you'll see it runs a scan and picks up the FPGA and programmable

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Read-Only memory located on the board.

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So I go ahead and browse and I want to browse to my one of my desktop lab three folder and the US are

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indoor basically the project directory for the IAC so we can navigate to this U.S. Arbet file which

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is what we want to get open that up and you might get a warning on here something about the clock don't

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that's OK.

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Yes.

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And then you want to hit this program button and you might get another warning if you do it.

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Yes.

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And you'll see the status Elodie on your basis to ward flash back and forth.

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But you know that it's programming and you'll get a note down here saying preparing to program programming

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and programming successfully so it looks like it's successfully simulated.

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So at this point you should be able to view the demo video and basically implement the same functionality

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that I was doing on there.

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And now at this point you've successfully completed lab 3 so go ahead get ready and start lab for.