Index of /files/Udemy/Udemy - Learn VHDL and FPGA Development 2018-8/

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1. Contact Information/                            26-Aug-2023 17:11                   -
10. Xilinx Tools/                                  26-Aug-2023 17:11                   -
11. Lab 1 - Full Adder/                            26-Aug-2023 17:11                   -
12. Lab 2 - Shift Register/                        26-Aug-2023 17:11                   -
13. Lab 3 - Universal Shift Register/              26-Aug-2023 17:11                   -
14. Lab 4 - 7 Segment Display/                     26-Aug-2023 17:11                   -
15. Lab 5 - Counter/                               26-Aug-2023 17:11                   -
16. Lab 6 - Multiplier/                            26-Aug-2023 17:11                   -
17. Lab 7 - RC Servo/                              26-Aug-2023 17:11                   -
18. Lecture Notes/                                 26-Aug-2023 17:11                   -
19. Extra References/                              26-Aug-2023 17:11                   -
2. Introduction/                                   26-Aug-2023 17:11                   -
3. VHDL Data Types/                                26-Aug-2023 17:11                   -
4. VHDL Syntax/                                    26-Aug-2023 17:11                   -
5. VHDL Coding Structure/                          26-Aug-2023 17:11                   -
6. Test Bench/                                     26-Aug-2023 17:11                   -
7. Implementing State Machines in VHDL/            26-Aug-2023 17:11                   -
8. FPGA Development Boards/                        26-Aug-2023 17:11                   -
9. Altera Tools/                                   26-Aug-2023 17:11                   -