WEBVTT 00:01.190 --> 00:07.200 Go Welcome to the fab three solutions video in this video one will walk you through the steps needed 00:07.200 --> 00:09.630 to complete lab 3. 00:09.720 --> 00:16.350 So in the lab 3 section there is a zip file lab three which you go ahead and download and unzip which 00:16.350 --> 00:17.950 I've done here on a desktop. 00:17.950 --> 00:24.810 Then when you zip that there you will see there are there is a folder called tests a score bench on 00:24.810 --> 00:26.480 a score Ellaby. 00:26.490 --> 00:31.920 This is contains a home a library package it'll be used in your test bench. 00:31.920 --> 00:32.930 Don't worry about it. 00:33.090 --> 00:36.870 However make sure you don't delete it otherwise your testbench will simulate. 00:36.900 --> 00:43.430 So just leave that folder go in and make sure you keep the structure the same that's very important. 00:44.010 --> 00:51.570 As far as the DCL script I give you know we've got this U.S. Our folder which if you go and open that 00:51.570 --> 00:55.970 up that's what contains your VH DL file. 00:56.090 --> 01:06.810 The US are the HD filer here and TACL script your test bench your test us are an input output which 01:06.830 --> 01:08.280 are CXXVI files. 01:08.300 --> 01:16.510 These were your testbench uses and you get your lab 3 tasks which will open up here. 01:16.740 --> 01:24.590 And as you can see we've got four different tasks here for lap three tasks one is to complete the U.S. 01:25.260 --> 01:33.720 HD file by filling in question marks and then we want to create a Mollison project using module 7.1 01:33.940 --> 01:37.300 as a reference to successfully simulate your just your design. 01:37.680 --> 01:46.140 Then after we successfully simulate it model Sam will want to create a project in Xilinx C and to create 01:46.150 --> 01:55.380 a file that will use that file to load onto the FPGA and verify that everything's working as expected. 01:55.380 --> 01:55.670 All right. 01:55.680 --> 02:04.580 So for the first task is to simulate or fix essentially the the US or file the VHDL file. 02:04.680 --> 02:07.880 So what I want to do is go ahead and. 02:08.030 --> 02:16.320 OK I'll go into this us our folder here in your lab three directory and go ahead and open that up I'm 02:16.320 --> 02:18.990 going to do these edits with notepad plus plus. 02:19.050 --> 02:23.730 You can do them with any editor really you could even use just regular notepad. 02:23.750 --> 02:32.400 However I like Notepad plus plus because you can select your language to VHDL and there it picks up 02:32.400 --> 02:38.090 on that and explain syntax and gives you a different color so you can kind of note between keywords 02:38.250 --> 02:40.230 and comments and everything else. 02:40.230 --> 02:44.930 So here's our US our VHDL file. 02:46.020 --> 02:53.430 So I'll give you the task by label and here in the file and some comments and then go to our libraries 02:53.430 --> 02:54.620 or entity. 02:54.900 --> 03:00.190 And if you go through you'll see I've got this a sequel to this question mark. 03:00.450 --> 03:04.120 Well these are basically you've got to go through and figure out what these are. 03:04.140 --> 03:09.300 So first thing to do is we're going to go ahead and open up models because this is typically the the 03:09.300 --> 03:11.710 process I'll go through in order to solve this. 03:11.760 --> 03:16.590 So we open up model Sam we've got to file new. 03:16.590 --> 03:23.280 Are we going to file change directory and we want to navigate to that U.S. our directory which is in 03:23.280 --> 03:25.710 the fab 3 folder us our. 03:25.800 --> 03:34.590 I click OK and yes see your transcript window kind of telling you what's going on and to file new library 03:35.130 --> 03:41.580 because anytime you create a change your directory in your work with models you have to have a library. 03:41.580 --> 03:44.710 This is where it stores the simulations and everything. 03:44.760 --> 03:49.740 You only have to do this once if you open this directory up later on. 03:49.770 --> 03:53.880 And it's you still have the library called work which I'll show you here once. 03:54.450 --> 03:58.640 So you just want to select a new library and a logical mapping to it. 03:58.740 --> 04:02.820 And the default is work which is fine that's just what I leave my house. 04:02.820 --> 04:04.320 Go ahead click OK. 04:04.710 --> 04:11.930 And if we open up go to this directory here you'll see we've got this lab three US are. 04:12.330 --> 04:19.050 We've got this Madison configuration settings file and it creates this work folder which we go into 04:19.050 --> 04:19.520 there. 04:19.540 --> 04:23.700 There's just that's where when we simulate it's going to store all that data in there. 04:23.760 --> 04:26.340 So that's all that's really doing. 04:26.430 --> 04:26.720 All right. 04:26.790 --> 04:31.500 So now we're going to go ahead and we're going to attempt to simulate this. 04:31.710 --> 04:41.490 So I'll go to my tools TCO execute macro and you want to select that you start PCL file that is included 04:41.490 --> 04:45.050 in your lab lab 3 former structures. 04:45.060 --> 04:50.790 Go ahead and select that and it's going to tell you which this is where you get the transcript down 04:50.790 --> 04:51.560 here. 04:51.750 --> 04:54.610 It's saying it's got some errors. 04:55.410 --> 05:01.990 And this is where it's telling you and then your USRA HD file line 47 and there is a syntax error. 05:02.240 --> 05:07.010 And so if you go into here line 47 had picked it up. 05:07.070 --> 05:14.480 It does not recognize what that question mark is and because questionmark is not is not defined basically 05:14.480 --> 05:15.070 so. 05:15.310 --> 05:16.530 And that's why I did that. 05:16.530 --> 05:20.220 They are designed to make you go through and hopefully figure all this out. 05:20.480 --> 05:26.230 So ok for this line 47 it's telling us we need to sign the output to what. 05:26.510 --> 05:28.240 Well if you look here. 05:29.460 --> 05:35.280 We're going to sign that to a wretch because we can't read what the value of a is. 05:35.300 --> 05:43.900 And so we're going to have this signal a ridge that we modify and associate it with this output. 05:44.390 --> 05:51.050 So to solve that we'll go ahead and type in the range and as you'll see it will pull up a little box 05:51.050 --> 05:57.500 saying all they read is that what you want to use and yes we do hit enter and so no that that should 05:57.500 --> 06:03.580 be fixed so let's go ahead and go to the transfer window a model sim right click clear. 06:03.590 --> 06:12.530 That clears it out and we'll go Hago tools DCL execute macro while we execute it and see we still got 06:12.530 --> 06:13.060 more errors. 06:13.070 --> 06:17.200 But exactly that was a problem I didn't save it. 06:17.240 --> 06:23.030 So you had to go through here and it still picked up on the error on line 47 because we didn't say this 06:23.030 --> 06:24.940 so it hit save. 06:24.960 --> 06:27.620 We'll go for it I get it real quick I'll clear that. 06:27.620 --> 06:34.610 Go to Tools to C-L execute macro or us are TCO. 06:34.980 --> 06:40.470 And now it's saying we've got an error on line 53 and got 69 75. 06:40.470 --> 06:46.050 However typically this isn't all the errors like Usually after picks up one or two errors it'll just 06:46.050 --> 06:54.480 exit because at that point it doesn't know what's going on so you open this up and we'll go to line 06:54.490 --> 06:57.080 53 that's for the next areas right here. 06:57.090 --> 06:59.000 It doesn't recognize that questionmark again. 06:59.370 --> 07:01.600 So we've got to go through this. 07:02.070 --> 07:10.760 And so far I hear basically this is a VHDL process and we want this to be evaluated on every clock cycle. 07:10.770 --> 07:16.050 So what do we need to put insensitively less we need to put the clock signal and the sensitivity list 07:16.500 --> 07:23.040 which appear in our entity declaration is our clock has to find us. 07:23.090 --> 07:23.770 OK. 07:23.940 --> 07:32.160 So if I go ahead and put C OK in there and then I want to save and I'll run through this one more time. 07:32.160 --> 07:44.820 Clear your transcript models then go to Tools TCO execute macro select the TC file again open and now 07:44.820 --> 07:51.420 it's telling us on line 58 and basically outhe's continue this process until eventually a model some 07:51.420 --> 07:54.750 will go ahead or compile everything when all of the errors are gone. 07:54.970 --> 08:01.320 All these question marks in and you see a note saying that you successfully simulated the US are so 08:01.320 --> 08:05.030 we're going to go ahead and just go through I just did the first C like that just to kind of create 08:05.050 --> 08:07.570 the process I usually go through. 08:08.280 --> 08:17.130 So as we go down here to line 58 we're in a reset process so on every clock edge we're checking to see 08:17.130 --> 08:22.560 if the reset is one or if it's being pressed and if it is being pressed we want to set a red edge to 08:22.560 --> 08:27.240 zero because every edge is tied to AA which is our output. 08:27.240 --> 08:30.560 So if I go ahead I'll just put a zero in there. 08:30.690 --> 08:37.150 That should fix that air will save more to keep on moving down and then we'll attempt to see if we if 08:37.150 --> 08:38.640 we got this right. 08:38.640 --> 08:46.740 So now this case statement is evaluating the signal s which appear on our input. 08:46.740 --> 08:49.220 Here is a standard logic vector one down at zero. 08:49.230 --> 08:52.040 That's two bits and representative. 08:52.040 --> 08:56.030 If it's a 0 0 with both bits are low we want to hold. 08:56.340 --> 09:00.420 Well for one to whole we want every edge to be a red again. 09:00.480 --> 09:06.420 So where just put a edge there that hopefully should solve that air. 09:06.460 --> 09:09.060 Now we have this whole right shift process. 09:09.060 --> 09:11.210 This is where we got to 0 1. 09:11.220 --> 09:17.170 We want to shift everything to the right and so we're shifting everything to the right. 09:17.190 --> 09:24.390 If you think about it the the far left most bit is going to be the state or with which we have set as 09:24.390 --> 09:31.050 a minus one which is a 7 a ridge on a 7 is the MSP most significant bit. 09:31.050 --> 09:33.310 We want that to be zero. 09:33.630 --> 09:37.000 Because you are shifting over we're basically filling in zeros. 09:37.050 --> 09:42.260 So in order to make that zero 0 0 there. 09:42.780 --> 09:48.170 Now note I have to put if I follow up I would just leave this like that as a zero. 09:48.180 --> 09:52.120 This would give me an error which I'll go ahead and show you here. 09:52.230 --> 09:54.970 We'll save here. 09:55.190 --> 09:57.560 Clear tools. 09:57.560 --> 10:00.310 Just yell execute macro. 10:00.390 --> 10:08.030 Us are open that up and line 66 is tell us we got there and that's right here. 10:08.210 --> 10:15.670 That's because I need to put those apostrophes on your side of it as you can see here down on line 73. 10:15.880 --> 10:16.480 There's. 10:16.730 --> 10:18.010 I've got those apostrophes on it. 10:18.010 --> 10:20.250 And that's because the standard logic vector. 10:20.360 --> 10:22.820 If this was an integer that would be OK. 10:22.850 --> 10:28.590 So I've got to put these different apostrophes in there and that. 10:28.610 --> 10:35.350 Now that should except that if I clear tools to execute macro 10:38.580 --> 10:42.340 and that's and that's the process this is a process I want you to use and you go through here. 10:42.360 --> 10:47.180 So now it's time we've got to err on line 69 which we know because we haven't figured this out. 10:47.190 --> 10:55.690 So now we need to determine OK we're in the right shift process so we went and we took our leftmost 10:55.740 --> 10:57.450 bit made that a zero. 10:57.450 --> 11:02.790 Now we need to make the rest of them equal to what the previous ones were before and basically just 11:02.790 --> 11:09.290 shifted over and essentially you can just use his left shift process as a as a reference. 11:09.300 --> 11:16.270 So over here we're going to want to make this equal to a ridge or dedo. 11:16.850 --> 11:30.520 That's our generic minus one down to one and then therefore basically we're taking all this data with 11:30.520 --> 11:33.400 two here and we're doing our right shift with it. 11:33.460 --> 11:43.040 So save that and then we've got on this line 75 here a serial load. 11:43.290 --> 11:43.580 OK. 11:43.650 --> 11:44.620 So you want to load. 11:44.640 --> 11:46.320 This is where we load values in. 11:46.500 --> 11:52.530 So we're going to loaded it on a registry and we determine what what value do we want to load in. 11:52.530 --> 11:56.290 Well what's our input entity value our input into the value. 11:56.370 --> 12:08.020 Is this I instead logic school for make that and I go ahead and save now see let's try and simulate 12:08.140 --> 12:09.070 this. 12:09.150 --> 12:09.470 OK. 12:09.500 --> 12:13.230 Tools you know execute macro. 12:13.270 --> 12:19.430 Open that up and OK everything compiled successfully and voila. 12:19.570 --> 12:20.630 You see we get this note. 12:20.630 --> 12:23.330 No success us our test completed. 12:23.660 --> 12:26.720 So I'll go ahead right click zoom fool. 12:26.800 --> 12:33.430 You can see all all the way form everything that's going on here which is a little bit difficult to 12:33.430 --> 12:34.230 read. 12:34.600 --> 12:39.370 You can sit here and go through all these toggling a clock cycles and making sure that all your bits 12:39.370 --> 12:41.780 are shifting as as expected. 12:41.890 --> 12:47.440 But when you get the more complex designs this really is not not what you want to be doing. 12:47.440 --> 12:54.490 So typically it does have as you get more advanced you'll learn how to write test benches and inside 12:54.490 --> 12:59.770 a test bench if everything works as expected you'll get this note saying success. 13:00.040 --> 13:04.980 And usually in design process you have a separate engineer who will create the test bench. 13:05.180 --> 13:11.670 That's compared to you and then that way if if his test bench successfully completes your design then 13:11.680 --> 13:15.150 you say that your design is verified and ready to go. 13:15.230 --> 13:16.720 So all right. 13:16.720 --> 13:19.540 So we've got that we've got the first two steps completed. 13:19.540 --> 13:25.300 We went ahead and we completed the lab we successfully all the question marks in our code. 13:25.300 --> 13:32.500 We went through and got it to compile successfully and we were able to successfully simulate and model 13:32.570 --> 13:33.350 them. 13:33.610 --> 13:37.360 And that's usually the flow you're going to want to use with all the rest of. 13:37.410 --> 13:39.240 Right here you're going to probably end up. 13:39.330 --> 13:45.040 And that's why I give you this DCL scripts you're going to be having an editor like Notepad or whatever 13:45.040 --> 13:51.750 you're using to edit these files and you're going to edit them save your tools TCO. 13:52.270 --> 13:57.430 Run a macro run the macro script and just keep reading the transcript they're just going to tell you 13:57.640 --> 14:02.740 the line where your errors are at and just keep following that until you get to successfully simulate 14:02.740 --> 14:03.210 this. 14:03.200 --> 14:11.490 So all right our next step is we want to go ahead and create a project in ISC. 14:11.560 --> 14:13.090 So go ahead. 14:14.080 --> 14:19.710 All right so now that we've completed our model sim simulation we want to go ahead and create our Xilinx 14:19.710 --> 14:20.770 science project. 14:20.770 --> 14:27.140 So go ahead and bring up the IAC and you'll see the screen here. 14:27.220 --> 14:34.670 We're going to go ahead and click on the new project and we want to go ahead and navigate to another 14:34.680 --> 14:35.610 location. 14:38.710 --> 14:48.160 Navigate to our lab three and click on the US are opened up and then give with the name we just want 14:48.160 --> 14:49.610 to want to make it. 14:49.960 --> 14:55.050 USRA because that's the same name as the entity which is just good practice to do so. 14:55.350 --> 15:03.540 Click next and you want to select all the project settings that are tied to the FPGA you're targeting 15:04.050 --> 15:12.930 which were targeting a Spartan 3 on the basis to board which is the device ex-chief 3 x 100 the package 15:12.930 --> 15:15.630 C.P. 1 3 2 SPI dash 4. 15:15.680 --> 15:20.730 If you're using any other type of development board you'll find all this information located in the 15:20.730 --> 15:24.320 User Guide or even if you look at the board itself. 15:24.730 --> 15:31.020 The FPGA chapel typically have to have a part number on there you can look that up online and figure 15:31.020 --> 15:32.010 all this information for here. 15:32.010 --> 15:36.930 Most of the stuff once you select these first five different values the rest is here you can pretty 15:36.930 --> 15:40.120 much leave as as our state are so good. 15:40.140 --> 15:45.360 Next gives your project summary finish. 15:45.450 --> 15:47.890 And here we've got an empty project. 15:47.920 --> 15:57.090 The US are going to go ahead and select the project add source and got to go back one level to find 15:57.150 --> 15:58.470 this US R-FL. 15:58.590 --> 16:05.400 Now since we went ahead and successfully simulated this a model said there should be no problems with 16:05.400 --> 16:06.120 this workings. 16:06.120 --> 16:08.730 Why not go ahead and add the source file. 16:09.210 --> 16:12.180 If I double click it give me. 16:12.180 --> 16:16.870 You'll note it should have picked up all the different as you can see we've got a ridge there picked 16:16.880 --> 16:19.770 up all the different changes we made on it there. 16:19.830 --> 16:26.400 So if we had not made those changes and mouse them and we try to synthesize this it would give you errors 16:26.550 --> 16:28.680 and you could debug down here. 16:28.680 --> 16:32.030 However you could have it wouldn't stick. 16:32.070 --> 16:35.010 It might not necessarily work well it's going to do is tell you this. 16:35.100 --> 16:37.320 Syntactically it's correct. 16:37.320 --> 16:39.520 It just it may not be doing what you want it to do. 16:39.540 --> 16:46.800 Like we could tie this a two we can make it it had a second signal one here and tie it to that and change 16:46.800 --> 16:47.960 it or. 16:48.120 --> 16:50.350 The biggest problem would be in this right shift left shift. 16:50.370 --> 16:52.560 We could mess that up. 16:52.560 --> 17:00.750 We could say OK instead of data register with minus one and make it data register with minus 2 and so 17:00.750 --> 17:05.130 on and so forth then we could have something that works be thrown on the board it doesn't do what you 17:05.130 --> 17:05.600 want. 17:05.610 --> 17:18.480 So OK so now we need to add the U.S. file to a project source and then all us our. 17:18.710 --> 17:23.100 So here you go up to the lab three the top level you've got that this U.S. file. 17:23.110 --> 17:25.490 I want to go ahead and select Open on that. 17:25.670 --> 17:26.930 OK. 17:26.930 --> 17:32.270 And now you expand this down and you want to make sure that your the HD files are top level which has 17:32.270 --> 17:40.250 this three triangle type of thing going on with double click or you see efile you can see we've got 17:40.340 --> 17:46.850 now in our beach do you we've got a which is a standard logic vector data with one minus one down to 17:46.850 --> 17:48.580 zero in our data with a. 17:48.590 --> 17:56.900 So it's a standard logic vector 7 down to zero which if we go all you use in order to associate each 17:56.900 --> 18:00.680 one of those values we've got a zero through a seven. 18:00.680 --> 18:11.090 So we're tying a zero to location 5 which like in the User Guide and 5 is a good output to an LCD on 18:11.090 --> 18:12.780 the basics to board. 18:13.340 --> 18:18.420 And all right so now we've got all the files we need in here. 18:18.560 --> 18:23.630 So we got to select our U.S. our behavior VHDL file. 18:23.630 --> 18:30.440 You'll notice if I select this us our ECF file it doesn't give you options to generate a bit file because 18:30.810 --> 18:33.870 you can't generate it with just that you need a VHDL file. 18:34.100 --> 18:38.200 So we select that and it gives us all these options down here we can do. 18:38.200 --> 18:45.020 So we want to go to implement design right click run and I'll tell you it's running self-assess it's 18:45.020 --> 18:50.960 going through and synthesizing and checking and syntactically making sure that everything is correct 18:50.960 --> 18:57.060 which if you got to simulate correctly in Madison this should be working no problem. 18:57.230 --> 19:02.630 You may get a few warnings telling you that your software subscription period has lapsed. 19:02.630 --> 19:05.500 However if you just recently download the probably won't see this warning. 19:05.510 --> 19:11.000 I've I've had the software on my computer for several years so that's why it's giving me a warning but 19:12.680 --> 19:15.740 it's nothing nothing major If you see that don't worry about it. 19:16.220 --> 19:19.250 Then the next thing one is generates the programming file. 19:19.250 --> 19:21.890 Go ahead and click run. 19:22.790 --> 19:28.920 And this is going to create our top file which is the actual file We're going to load onto the FPGA. 19:29.240 --> 19:34.860 So once you create and that's a staggering check saying that that's that's good. 19:34.880 --> 19:38.460 Once you create this file you can literally take this file anywhere. 19:38.540 --> 19:42.620 You can e-mail it to someone and they can load onto their FPGA because that contains everything it ties 19:42.620 --> 19:44.830 in this VHDL file. 19:44.830 --> 19:51.590 This design turns it all into the logic gates that it synthesizes to and this file and ties all these 19:51.590 --> 19:55.500 inputs and outputs to physical pins located on the FPGA. 19:55.670 --> 19:59.460 And that's that's that's the thing we want we want that program file. 19:59.600 --> 20:01.290 So that's generated. 20:01.400 --> 20:08.010 We can go ahead and minimize that number want to open up a dept before you do that. 20:08.060 --> 20:16.180 Make sure that on your bases to board your jumper 3 is there is PC and Rom make your on PC. 20:16.190 --> 20:21.350 This does you need this to be connected otherwise your computer won't recognize the board and you will 20:21.350 --> 20:22.680 bear load any files on it. 20:22.730 --> 20:27.840 So make sure selected the PC power on and plug it into your computer. 20:27.890 --> 20:33.050 Open up it dept and you should see something similar to this now. 20:33.410 --> 20:35.990 Right now it says no device is identified. 20:36.200 --> 20:43.640 So go ahead and click initialized chain and you'll see it runs a scan and picks up the FPGA and programmable 20:43.640 --> 20:45.580 Read-Only memory located on the board. 20:45.890 --> 20:54.440 So I go ahead and browse and I want to browse to my one of my desktop lab three folder and the US are 20:55.040 --> 21:01.520 indoor basically the project directory for the IAC so we can navigate to this U.S. Arbet file which 21:01.520 --> 21:08.660 is what we want to get open that up and you might get a warning on here something about the clock don't 21:08.760 --> 21:09.750 that's OK. 21:09.880 --> 21:10.900 Yes. 21:10.970 --> 21:15.740 And then you want to hit this program button and you might get another warning if you do it. 21:15.840 --> 21:16.840 Yes. 21:17.420 --> 21:21.780 And you'll see the status Elodie on your basis to ward flash back and forth. 21:21.780 --> 21:27.110 But you know that it's programming and you'll get a note down here saying preparing to program programming 21:27.110 --> 21:31.390 and programming successfully so it looks like it's successfully simulated. 21:31.520 --> 21:39.290 So at this point you should be able to view the demo video and basically implement the same functionality 21:39.290 --> 21:40.810 that I was doing on there. 21:41.180 --> 21:49.580 And now at this point you've successfully completed lab 3 so go ahead get ready and start lab for.