Index of /files/Udemy/Udemy - High-Level Synthesis for FPGA, Part 3 - Advanced 2023-1/7 - AXI in HLS/

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37 - AXIInHLS-Introduction.mp4                     26-Jan-2023 07:44            14563597
37 - Introduction.mp4                              26-Jan-2023 07:44            23987599
38 - AXIInHLS-MemoryMappedInterface-Quiz-Soluti..> 26-Jan-2023 07:44              122963
38 - Memory Mapped Interface.mp4                   26-Jan-2023 07:44            28184852
39 - AXI Protocol.mp4                              26-Jan-2023 07:44            55470926
39 - AXIInHLS-AXI-Protocol-Quiz-Solution.pdf       26-Jan-2023 07:44              113747
40 - AXIInHLS-memory-mapped-output-01-Quiz-Solu..> 26-Jan-2023 07:44               93788
40 - Memory Mapped Output 01.mp4                   26-Jan-2023 07:44           127507834
40 - memory-mapped-output-01.zip                   26-Jan-2023 07:44                7306
41 - AXI Addressing in Vivado.mp4                  26-Jan-2023 07:44            40957654
41 - AXIInHLS-AXI-Addressing-Vivado-Quiz-Soluti..> 26-Jan-2023 07:44               97165
42 - AXIInHLS-memory-mapped-output-02-Quiz-Solu..> 26-Jan-2023 07:44               98310
42 - Memory Mapped Output 02.mp4                   26-Jan-2023 07:44           100281645
42 - memory-mapped-output-02.zip                   26-Jan-2023 07:44                7801
43 - AXIInHLS-memory-mapped-IO-Quiz-Solution.pdf   26-Jan-2023 07:44               97729
43 - Memory Mapped IO.mp4                          26-Jan-2023 07:44           116329211
43 - memory-mapped-IO.zip                          26-Jan-2023 07:44                7234
44 - AXIInHLS-m-AXI4-Quiz-Solution.pdf             26-Jan-2023 07:44              108422
44 - The maxi interface.mp4                        26-Jan-2023 07:44           161785587
44 - m-AXI4.zip                                    26-Jan-2023 07:44                9601
45 - Exercises.html                                26-Jan-2023 07:44                 320