PWM Project Status
Project File: Tilt_Sensor_Interface.xise Parser Errors: No Errors
Module Name: PWM Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 44 1,920 2%  
Number of 4 input LUTs 19 1,920 1%  
Number of occupied Slices 34 960 3%  
    Number of Slices containing only related logic 34 34 100%  
    Number of Slices containing unrelated logic 0 34 0%  
Total Number of 4 input LUTs 63 1,920 3%  
    Number used as logic 19      
    Number used as a route-thru 44      
Number of bonded IOBs 3 83 3%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.67      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Apr 20 16:12:19 201701 Warning (1 new)0
Translation ReportCurrentThu Apr 20 16:12:27 2017000
Map ReportCurrentThu Apr 20 16:12:32 2017002 Infos (2 new)
Place and Route ReportCurrentThu Apr 20 16:12:41 2017003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Apr 20 16:12:43 2017005 Infos (5 new)
Bitgen ReportCurrentThu Apr 20 16:12:52 2017000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu Apr 20 16:12:52 2017
WebTalk Log FileCurrentThu Apr 20 16:12:53 2017

Date Generated: 04/20/2017 - 19:02:17