ALU_Top Project Status (04/20/2017 - 19:06:04)
Project File: ALU.xise Parser Errors: X 1 Error
Module Name: ALU_Top Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
145 Warnings (0 new)
Design Goal:  
  • Routing Results:
All Signals Completely Routed
Design Strategy:
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 372 1,920 19%  
Number of 4 input LUTs 912 1,920 47%  
Number of occupied Slices 547 960 56%  
    Number of Slices containing only related logic 547 547 100%  
    Number of Slices containing unrelated logic 0 547 0%  
Total Number of 4 input LUTs 987 1,920 51%  
    Number used as logic 912      
    Number used as a route-thru 75      
Number of bonded IOBs 38 83 45%  
Number of BUFGMUXs 2 24 8%  
Average Fanout of Non-Clock Nets 3.46      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Apr 20 19:04:58 20170145 Warnings (0 new)6 Infos (0 new)
Translation ReportCurrentThu Apr 20 19:05:12 2017000
Map ReportCurrentThu Apr 20 19:05:18 2017002 Infos (0 new)
Place and Route ReportCurrentThu Apr 20 19:05:35 2017003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Apr 20 19:05:38 2017005 Infos (0 new)
Bitgen ReportCurrentThu Apr 20 19:05:58 2017000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateThu Apr 20 19:05:58 2017
WebTalk Log FileOut of DateThu Apr 20 19:06:04 2017

Date Generated: 04/20/2017 - 19:18:12