ALU_Top Project Status (04/21/2017 - 18:22:10)
Project File:	Booths_Algorithm.xise	Parser Errors:	No Errors
Module Name:	ALU_Top	Implementation State:	Programming File Generated
Target Device:	xc3s100e-4cp132	Errors:	No Errors
Product Version:	ISE 12.4	Warnings:	149 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	355	1,920	18%
Number of 4 input LUTs	740	1,920	38%
Number of occupied Slices	465	960	48%
Number of Slices containing only related logic	465	465	100%
Number of Slices containing unrelated logic	0	465	0%
Total Number of 4 input LUTs	810	1,920	42%
Number used as logic	740
Number used as a route-thru	70
Number of bonded IOBs	35	83	42%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	3.34

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Apr 21 18:21:20 2017	0	149 Warnings (0 new)	32 Infos (0 new)
Translation Report	Current	Fri Apr 21 18:21:29 2017	0	0	0
Map Report	Current	Fri Apr 21 18:21:34 2017	0	0	2 Infos (0 new)
Place and Route Report	Current	Fri Apr 21 18:21:52 2017	0	0	4 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Fri Apr 21 18:21:55 2017	0	0	5 Infos (0 new)
Bitgen Report	Current	Fri Apr 21 18:22:05 2017	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Fri Apr 21 18:22:05 2017
WebTalk Log File	Current	Fri Apr 21 18:22:10 2017

Date Generated: 04/21/2017 - 18:22:10