Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.4 (WebPack) - M.81d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s100e
Project ID (random number) a58fbea0c9e9413b814544de1c078e64.E4EBC06448E04629A23451C1E121BDE4.2 Target Package: cp132
Registration ID 0_0_616 Target Speed: -4
Date Generated 2017-04-21T18:33:20 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2630QM CPU @ 2.00GHz CPU Speed 1995 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 27-bit up counter=1
 ROMs=4
  • 16x7-bit ROM=4
 Registers=20
  • Flip-Flops=20
 Xors=1
  • 1-bit xor4=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=15
  • AGG_IO=15
  • AGG_SLICE=49
  • NUM_4_INPUT_LUT=77
  • NUM_BONDED_IBUF=3
  • NUM_BONDED_IOB=12
  • NUM_BUFGMUX=2
  • NUM_CYMUX=33
  • NUM_LUT_RT=26
  • NUM_SLICEL=49
  • NUM_SLICE_FF=47
  • NUM_XOR=27
 		NetStatistics
  • NumNets_Active=119
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=24
  • NumNodesOfType_Active_CNTRLPIN=24
  • NumNodesOfType_Active_DOUBLE=129
  • NumNodesOfType_Active_DUMMY=222
  • NumNodesOfType_Active_DUMMYESC=3
  • NumNodesOfType_Active_GLOBAL=13
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_HUNIHEX=3
  • NumNodesOfType_Active_INPUT=274
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_OMUX=118
  • NumNodesOfType_Active_OUTPUT=101
  • NumNodesOfType_Active_PREBXBY=67
  • NumNodesOfType_Active_VFULLHEX=6
  • NumNodesOfType_Active_VUNIHEX=6
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=2
  • NumNodesOfType_Vcc_PREBXBY=1
  • NumNodesOfType_Vcc_VCCOUT=3
 SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=6
  • IOB-DIFFS=5
  • SLICEL-SLICEM=22
 		SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • IBUF=3
  • IBUF_INBUF=3
  • IBUF_PAD=3
  • IOB=12
  • IOB_OUTBUF=12
  • IOB_PAD=12
  • SLICEL=49
  • SLICEL_C1VDD=1
  • SLICEL_CYMUXF=17
  • SLICEL_CYMUXG=16
  • SLICEL_F=40
  • SLICEL_F5MUX=7
  • SLICEL_FFX=24
  • SLICEL_FFY=23
  • SLICEL_G=37
  • SLICEL_GNDF=16
  • SLICEL_GNDG=16
  • SLICEL_XORF=14
  • SLICEL_XORG=13
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:3]
 IOB
  • O1=[O1_INV:0] [O1:12]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:12]
 IOB_PAD
  • DRIVEATTRBOX=[12:12]
  • IOATTRBOX=[LVCMOS25:12]
  • SLEW=[SLOW:12]
 SLICEL
  • BX=[BX_INV:0] [BX:19]
  • BY=[BY:9] [BY_INV:0]
  • CE=[CE:2] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:16]
  • CLK=[CLK:24] [CLK_INV:0]
  • SR=[SR:22] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:17] [0_INV:0]
  • 1=[1_INV:0] [1:17]
 SLICEL_CYMUXG
  • 0=[0:16] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:7] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:24] [CK_INV:0]
  • D=[D:24] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:23] [INIT1:1]
  • FFX_SR_ATTR=[SRLOW:24]
  • LATCH_OR_FF=[FF:24]
  • SR=[SR:22] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:10] [SYNC:14]
 SLICEL_FFY
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:23] [CK_INV:0]
  • D=[D:23] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:20] [INIT1:3]
  • FFY_SR_ATTR=[SRLOW:22] [SRHIGH:1]
  • LATCH_OR_FF=[FF:23]
  • SR=[SR:21] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:10] [SYNC:13]
 SLICEL_XORF
  • 1=[1_INV:0] [1:14]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
 BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
 BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
 IBUF
  • I=3
  • PAD=3
 IBUF_INBUF
  • IN=3
  • OUT=3
 IBUF_PAD
  • PAD=3
 IOB
  • O1=12
  • PAD=12
 IOB_OUTBUF
  • IN=12
  • OUT=12
 IOB_PAD
  • PAD=12
 SLICEL
  • BX=19
  • BY=9
  • CE=2
  • CIN=16
  • CLK=24
  • COUT=16
  • F1=40
  • F2=26
  • F3=26
  • F4=18
  • G1=37
  • G2=24
  • G3=24
  • G4=24
  • SR=22
  • X=22
  • XB=1
  • XQ=24
  • Y=13
  • YQ=23
 SLICEL_C1VDD
  • 1=1
 SLICEL_CYMUXF
  • 0=17
  • 1=17
  • OUT=17
  • S0=17
 SLICEL_CYMUXG
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
 SLICEL_F
  • A1=40
  • A2=26
  • A3=26
  • A4=18
  • D=40
 SLICEL_F5MUX
  • F=7
  • G=7
  • OUT=7
  • S0=7
 SLICEL_FFX
  • CE=2
  • CK=24
  • D=24
  • Q=24
  • SR=22
 SLICEL_FFY
  • CE=2
  • CK=23
  • D=23
  • Q=23
  • SR=21
 SLICEL_G
  • A1=37
  • A2=24
  • A3=24
  • A4=24
  • D=37
 SLICEL_GNDF
  • 0=16
 SLICEL_GNDG
  • 0=16
 SLICEL_XORF
  • 0=14
  • 1=14
  • O=14
 SLICEL_XORG
  • 0=13
  • 1=13
  • O=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s100e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s100e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s100e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s100e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s100e-cp132-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s100e-cp132-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
XSLTProcess 41 41 0 0 0 0 0
_impact 4 4 0 0 0 0 0
bitgen 51 51 0 0 0 0 0
cpldfit 41 41 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
hprep6 41 41 0 0 0 0 0
ibiswriter 1 1 0 0 0 0 0
map 49 49 0 0 0 0 0
ngc2edif 6 6 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 106 106 0 0 0 0 0
par 49 48 1 0 0 0 0
taengine 17 17 0 0 0 0 0
trce 48 48 0 0 0 0 0
tsim 41 41 0 0 0 0 0
xbash 1 1 0 0 0 0 0
xst 133 132 0 0 0 0 0
 
Help Statistics
Search words with results
adding bus ( 1 ) adding a bus ( 1 )
bus ( 1 ) bus tap ( 1 )
bus taps ( 1 ) counter ( 1 )
using bus taps ( 1 )
Help files
/doc/usenglish/isehelp/cpld_all/libs_le_buf.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_bufgsr.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_cb4ce.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_cb4cle.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_cb8re.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_cd4ce.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_cj4ce.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_cj8re.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_comp16.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_comp8.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_compm2.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_d2_4e.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_d4_16e.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_fd.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_fjkp.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_inv.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_ld.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_ld16.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_ld4.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_ldc.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_ldcp.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_ldp.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_m2_1e.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_m4_1e.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_nand2.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_nand7.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_nor2.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_sr4rled.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_xnor2.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_xnor7.htm ( 1 )
/doc/usenglish/isehelp/pim_r_supported_spi_bpi_proms.htm ( 1 ) /doc/usenglish/isehelp/pn_db_npw_device_properties.htm ( 1 )
/doc/usenglish/isehelp/pn_db_nsw_select_source_type.htm ( 1 ) /doc/usenglish/isehelp/spartan3e/libs_le_cb16ce.htm ( 1 )
/doc/usenglish/isehelp/spartan3e/libs_le_cb16cled.htm ( 1 ) /doc/usenglish/isehelp/spartan3e/libs_le_cb2cled.htm ( 1 )
/doc/usenglish/isehelp/spartan3e/libs_le_cb4ce.htm ( 1 ) /doc/usenglish/isehelp/spartan3e/libs_le_cb4cle.htm ( 1 )
/doc/usenglish/isehelp/spartan3e/libs_le_cc16ce.htm ( 1 ) /doc/usenglish/isehelp/spartan3e/libs_le_pullup.htm ( 1 )
/doc/usenglish/isehelp/spartan3e/libs_le_sr4ce.htm ( 1 ) /doc/usenglish/isehelp/spartan3e/libs_le_sr4cled.htm ( 1 )
/doc/usenglish/isehelp/sse_c_bus_names.htm ( 1 ) /doc/usenglish/isehelp/sse_c_name_nets_to_bus.htm ( 1 )
/doc/usenglish/isehelp/sse_c_nets.htm ( 1 ) /doc/usenglish/isehelp/sse_c_overview.htm ( 1 )
/doc/usenglish/isehelp/sse_db_net_attr_visibility.htm ( 1 ) /doc/usenglish/isehelp/sse_db_obsolete_symbols.htm ( 1 )
/doc/usenglish/isehelp/sse_n_adding_bus_tap.htm ( 1 ) /doc/usenglish/isehelp/sse_p_adding_bus_tap_autonaming.htm ( 1 )
/doc/usenglish/isehelp/sse_p_adding_bus_tap_manually.htm ( 1 ) /doc/usenglish/isehelp/sse_p_adding_net.htm ( 1 )
/doc/usenglish/isehelp/sse_p_connecting_net_bus.htm ( 1 ) /doc/usenglish/isehelp/sse_p_creating_bus.htm ( 1 )
/doc/usenglish/isehelp/sse_p_naming_bus.htm ( 1 ) /doc/usenglish/isehelp/sse_p_naming_net.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_ProjectDescription=16 bit LFSR implementation.
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2017-04-20T13:45:59 PROP_intWbtProjectID=E4EBC06448E04629A23451C1E121BDE4
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s100e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=cp132
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=4
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=2 NGDBUILD_NUM_FDC=15 NGDBUILD_NUM_FDE=4 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDR=27 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=1
NGDBUILD_NUM_LUT1=26 NGDBUILD_NUM_LUT3=8 NGDBUILD_NUM_LUT4=42 NGDBUILD_NUM_MUXCY=33
NGDBUILD_NUM_MUXF5=7 NGDBUILD_NUM_OBUF=12 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=27
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=15 NGDBUILD_NUM_FDE=4 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDR=27 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=2
NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=26 NGDBUILD_NUM_LUT3=8 NGDBUILD_NUM_LUT4=42
NGDBUILD_NUM_MUXCY=33 NGDBUILD_NUM_MUXF5=7 NGDBUILD_NUM_OBUF=12 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=27