LFSR_Top Project Status (04/21/2017 - 18:33:25)
Project File: Linear_Feedback_Shift_Register.xise Parser Errors: No Errors
Module Name: LFSR_Top Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
5 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 47 1,920 2%  
Number of 4 input LUTs 51 1,920 2%  
Number of occupied Slices 49 960 5%  
    Number of Slices containing only related logic 49 49 100%  
    Number of Slices containing unrelated logic 0 49 0%  
Total Number of 4 input LUTs 77 1,920 4%  
    Number used as logic 51      
    Number used as a route-thru 26      
Number of bonded IOBs 15 83 18%  
Number of BUFGMUXs 2 24 8%  
Average Fanout of Non-Clock Nets 3.19      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Apr 21 18:32:48 201704 Warnings (0 new)1 Info (0 new)
Translation ReportCurrentFri Apr 21 18:32:58 2017000
Map ReportCurrentFri Apr 21 18:33:01 2017002 Infos (0 new)
Place and Route ReportCurrentFri Apr 21 18:33:11 201701 Warning (0 new)4 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Apr 21 18:33:13 2017005 Infos (0 new)
Bitgen ReportCurrentFri Apr 21 18:33:20 2017000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri Apr 21 18:33:21 2017
WebTalk Log FileCurrentFri Apr 21 18:33:25 2017

Date Generated: 04/21/2017 - 18:33:25