BCD_Display_Top Project Status (04/21/2017 - 18:25:26)
Project File:	BCD_Display.xise	Parser Errors:	No Errors
Module Name:	BCD_Display_Top	Implementation State:	Programming File Generated
Target Device:	xc3s100e-4cp132	Errors:	No Errors
Product Version:	ISE 12.4	Warnings:	18 Warnings (1 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	160	1,920	8%
Number of 4 input LUTs	208	1,920	10%
Number of occupied Slices	168	960	17%
Number of Slices containing only related logic	168	168	100%
Number of Slices containing unrelated logic	0	168	0%
Total Number of 4 input LUTs	295	1,920	15%
Number used as logic	208
Number used as a route-thru	87
Number of bonded IOBs	15	83	18%
Number of BUFGMUXs	1	24	4%
Number of RPM macros	16
Average Fanout of Non-Clock Nets	3.35

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Apr 21 18:24:43 2017	0	17 Warnings (0 new)	2 Infos (0 new)
Translation Report	Current	Fri Apr 21 18:24:54 2017	0	0	0
Map Report	Current	Fri Apr 21 18:24:58 2017	0	0	3 Infos (0 new)
Place and Route Report	Current	Fri Apr 21 18:25:09 2017	0	1 Warning (1 new)	4 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Fri Apr 21 18:25:12 2017	0	0	5 Infos (0 new)
Bitgen Report	Current	Fri Apr 21 18:25:21 2017	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Fri Apr 21 18:25:21 2017
WebTalk Log File	Current	Fri Apr 21 18:25:25 2017

Date Generated: 04/21/2017 - 18:25:26