Potentiometer Interface

For the potentiometer interface assignment we are using the ADC capability of the FPGA or external ADC chip. The goal of this assignment is to take the ADC reading from the potentiometer and display it on a 4 digit 7 segment display. In order to successfully complete this assignment consider the following suggestions:

Verify that the binary to BCD design is working properly, this should have been completed from lab 1.

Verify that your Hex to 7 seg design is working correctly.

Double check that you are connect the potentiometer to the correct voltage rail, most FPGA board require 3.3V or 1.0V so be sure to double check this!

Setup

If your development board has a 4-digit on-board 7 segment display such as the BASYS 3 development board you can just use that. Otherwise you will need to connect an external 4 digit 7 segment display. See the schematic setup below:

See the BOM below for components I used during the demonstration of this lab.

Verification

To verify that your design is working properly you should see the 7 segment display go from 0000 to 4095 for a 12 bit ADC, this is because 2^12 = 4096 and we have to account for zero so we subtract 1 to get 4095. You may not get to exactly 4095, there will be some losses through resistors etc…

If you can display from 0 to above 3500, your design is working properly!