library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity top is
    Port ( clk,rst : in std_logic;
    up, load: in std_logic;
    loadin : in std_logic_Vector(7 downto 0);
    dout : out std_logic_Vector(7 downto 0)
    );
end top;

architecture Behavioral of top is
signal temp : std_logic_Vector(7 downto 0) := x"00";
begin
process(clk)
begin
if(rising_edge(clk)) then
  if(rst = '1') then
   temp  <= x"00";
    else
      if(load = '1') then
        temp <= loadin;
        else
                if(up = '1') then
                     temp <= temp + 1;
                else
                  temp <= temp - 1;
                end if;
      end if;
  end if;
end if;
end process;
dout <= temp;
end Behavioral;