WEBVTT 00:00.070 --> 00:06.200 Things become a bit complicated, as we use, if Elsie breaks there, we have a multiple of conditions 00:06.210 --> 00:09.260 to see that you cover all the possible combinations, right? 00:09.270 --> 00:15.660 So if you're just coming this out, OK, and invoke the code for the poorest one month's rate. 00:15.690 --> 00:22.920 Now here we have a medical condition, so let us first modify our food because now we are evaluating 00:22.920 --> 00:23.850 four inputs, right? 00:23.850 --> 00:26.280 So this should be written right down. 00:26.280 --> 00:34.380 You are now to see right now you could see the display now select is off, say, stupid crate, so sensitive 00:34.380 --> 00:36.430 of type and an endless corelogic, right? 00:36.480 --> 00:41.670 So it could have a nine possible logical rate, so we correctly define the behavior. 00:41.670 --> 00:48.150 Four zero zero zero one one zero one one My right and N3 present all the behavior that we have not mentioned 00:48.150 --> 00:48.510 with you. 00:48.810 --> 00:51.990 So if you just remove and L's from here, right? 00:52.230 --> 00:57.630 So rest of the combinations off select of simply undefined. 00:57.810 --> 01:01.450 So what system should do when we have a value, either? 01:01.470 --> 01:04.320 Then this conditions are not specified by a user. 01:04.800 --> 01:10.790 So this basically represents an incomplete behave, and this will again be leading to a creation of 01:10.790 --> 01:11.160 the let's. 01:11.370 --> 01:18.320 So if you just see a code and try to reload a schematic, you'll be able to see the extra circuitry 01:18.330 --> 01:20.130 which has been added to our design. 01:20.340 --> 01:25.890 And it also add a latch, which is something we never intended, right? 01:25.890 --> 01:30.150 So if you go to a schematic angle defining, we are expecting that chain of a Marxist. 01:30.540 --> 01:36.390 But along with the chain of matches, we again have this extraction up of MUX, which is indeed right, 01:36.390 --> 01:38.320 and the latter which is all to activate. 01:38.340 --> 01:44.130 Now, if you correctly specify the behavior, right, so forest, all the conditions, we want y to 01:44.940 --> 01:46.640 be simply close to zero, right? 01:46.650 --> 01:49.600 So this is this is a complete behavior. 01:49.770 --> 01:53.600 So we cover all the possible combinations that we want to go around. 01:53.610 --> 01:56.760 The rest of the combination will be simply to zero, right? 01:56.970 --> 02:00.930 So we specified the complete behavior for our system. 02:00.930 --> 02:04.910 In this case, we are correctly able to invoke a chain of right. 02:05.280 --> 02:12.230 If you just reload a schematic and you could go to a schematic now we correctly get a series of muxes. 02:12.480 --> 02:15.270 This is an expected silk right out of this. 02:15.810 --> 02:22.470 So remember this whether it is a fence with a two condition or a fence with a multiple coalitions c 02:22.470 --> 02:25.400 that you specify the complete behavior OK? 02:25.610 --> 02:33.780 As soon as you have any incomplete condition present in your design, Latch will be automatically added 02:33.900 --> 02:34.590 to your design. 02:34.800 --> 02:37.650 Latches are not actively supported by an SPG. 02:37.890 --> 02:42.090 OK, and that basically is considered bad for any bridges, right? 02:42.300 --> 02:45.390 So avoid the lattice and see that you complete. 02:45.600 --> 02:49.340 You add the complete definition for your system, right? 02:49.350 --> 02:55.480 So whenever you have a condition C that you mentioned the behavior of a system, well, condition worse, 02:56.490 --> 02:59.490 the system behavior when conditions do not break. 02:59.490 --> 03:06.210 So that is what we consider that the good holding practice when using it as T right now, what we going 03:06.210 --> 03:10.960 to do is we will try to consider some see circuit, right. 03:11.010 --> 03:16.830 So we have a good idea about how you use a false statement for implementation of the circuit that it 03:16.830 --> 03:20.850 just proceed and try to implement a few sequential circuit. 03:20.940 --> 03:26.700 OK, so that you have an understanding of how you use that little statement for an implementation of 03:26.700 --> 03:27.580 the sequences of.