WEBVTT 00:00.150 --> 00:06.390 Now, we already understood how we could add an expression to signal and put, now let's assume you 00:06.390 --> 00:12.030 want to assign an expression to a boat or a signal, depending on certain conditions. 00:12.070 --> 00:18.750 Then in that case, we have a two alternatives rate, so we either we could proceed to use a conditional. 00:19.930 --> 00:20.560 Signal. 00:21.750 --> 00:24.390 Statement did we already discussed? 00:26.360 --> 00:31.220 Or we could proceed with the selected. 00:33.170 --> 00:33.860 Signal. 00:35.540 --> 00:36.620 Street, right? 00:38.480 --> 00:44.450 So you could use them to choose, depending on the differing condition, which expression to be connected 00:44.450 --> 00:51.890 to the port or a signal, right, so they differ in we, they create an ideal schematic, but ultimately 00:51.890 --> 00:58.330 we will be performing a synthesis and then we invoke primitives that will be going on and FPGA, right? 00:58.350 --> 01:03.650 So even though the ideal schematic may be different, for example, conditional signals treatment. 01:03.680 --> 01:07.020 OK, so these include the chain of muxes. 01:07.020 --> 01:14.060 So when you observe the schematic that is a more detailed schematic, then you use a condition signal 01:14.060 --> 01:14.600 steedman. 01:14.810 --> 01:16.660 You'll be finding a kind of muxes. 01:16.670 --> 01:23.660 And that basically suggests that the way in which it operates like this, for example, let's assume 01:23.660 --> 01:27.980 we have like, OK, and then we want to connect it to any. 01:29.220 --> 01:32.130 OK, so he represented one of our input when. 01:33.240 --> 01:36.260 Let us assume select is zero, right? 01:36.540 --> 01:41.600 So this is the case else, we want to connect it to a b rated. 01:41.610 --> 01:44.820 This is the simple statement that we have written now. 01:44.820 --> 01:49.350 In this case, what will happen is as we start evaluating an expression. 01:49.350 --> 01:53.760 So first, we will verify whether conditions evaluate to true right. 01:53.760 --> 01:58.260 Save Select is equal to zero, so this condition will evaluate to true. 01:58.470 --> 02:05.610 In that case will be connecting why to any rate, so whatever value that we have on enabled will be 02:05.610 --> 02:11.070 simply sending it on y and the rest of the expression in this case will not be evaluating, right? 02:11.070 --> 02:16.920 So when we have a conditional signal statement, in that case, we go with the priority. 02:16.920 --> 02:22.320 So the expression which is specified first will be evaluated and if the condition that is specified 02:22.320 --> 02:27.390 evaluates to true y will be immediately assigned to that specific value. 02:27.510 --> 02:27.840 OK. 02:28.250 --> 02:31.180 The the rest of the conditions are simply not evaluated. 02:31.290 --> 02:31.540 Right. 02:31.560 --> 02:39.990 So if selected is not equal to zero, so this condition will fail, then only we check the next condition, 02:40.200 --> 02:40.500 right? 02:40.500 --> 02:46.470 So this is how we perform an evaluation on of a conditional signal statement, right? 02:46.470 --> 02:52.260 Whereas if you're going through the selected signals treatment rate, so we have a different format. 02:52.260 --> 02:53.300 So we started with. 02:53.760 --> 02:56.610 OK, for us, the condition is select. 02:56.610 --> 02:59.190 So we are select is right. 02:59.730 --> 03:02.180 So y will be equals to E. 03:02.400 --> 03:06.450 OK, then we have a value of zero. 03:07.650 --> 03:07.980 OK. 03:09.910 --> 03:16.330 Else it will be simply was to be right in this case, what will happen is to all the treatment will 03:16.330 --> 03:18.320 be evaluated in a bad light, right? 03:18.330 --> 03:23.950 So here if you consider the standard analytical logic typewriter, we have a water level. 03:24.370 --> 03:31.850 So in this case, what will happen is we will be verifying whether our expression is is equal to zero. 03:31.870 --> 03:36.760 If that is the case, if it is equal to zero, we will be connecting it to a rate. 03:36.760 --> 03:39.940 So all the multiple expression will be evaluated in pattern. 03:39.940 --> 03:46.270 So as soon as one of an efficient condition evaluates to true to that value will be a saying, and that 03:46.270 --> 03:48.100 is the only difference that we have, right? 03:48.370 --> 03:54.070 So here we will be getting a parallel kind of an architecture where all the conditions will be evaluated 03:54.520 --> 03:55.820 at the same instance. 03:55.850 --> 04:01.780 OK, so all the expression will be evaluated and the expression which evaluates to true. 04:02.410 --> 04:07.440 So the value of that value will be immediately assigned to the pool, right? 04:07.450 --> 04:13.630 Whereas if you consider the conditional signal assignment or conditional signal statement, in this 04:13.630 --> 04:17.870 case, we start with evaluation of an expression that is specified for. 04:17.890 --> 04:22.080 So if that evaluates to true, we won't be evaluating the rest of the expression, right? 04:22.090 --> 04:23.600 So this is the difference that we have. 04:23.890 --> 04:29.110 And ultimately, what will happen is so this won't be creating any performance difference, right? 04:29.170 --> 04:33.410 This is just the way of specifying an expression in and mutual right. 04:33.620 --> 04:40.150 Ultimately, if you observe the synthesis schematic, right, so the ideal that will be actually going 04:40.150 --> 04:45.760 on to an FPGA will be finding in both the cases, we get the same synthesis schematic, right? 04:45.760 --> 04:50.890 So in both the case, the logic that will be going on to an FPGA will remain the same rate. 04:51.310 --> 04:55.180 The only difference in this to Steedman is the way they evaluate and.