WEBVTT 00:00.480 --> 00:05.730 The next example that we're going to consider is a flight, and this will be primarily to discuss how 00:05.730 --> 00:12.270 we use the signal enough VW wondering right now if you observe the next which are different or have 00:12.270 --> 00:15.300 some need to sign with the help of the entity, right? 00:15.600 --> 00:19.100 So we'll be finding this natives on this. 00:19.200 --> 00:24.700 It is also totally different since we will be declaring yea, b and C OK. 00:24.870 --> 00:26.250 In an integer. 00:26.550 --> 00:30.420 Similarly, a sense zero will also be declaring an integer, right? 00:30.420 --> 00:32.880 So this note is also defined right. 00:33.360 --> 00:36.820 Then this two are also defined, right? 00:37.800 --> 00:41.730 Similarly, this is also defined and this one is also different, right? 00:42.540 --> 00:46.350 The rest of the notes are undefined in our system, right? 00:46.350 --> 00:51.360 So this net do not have any name attached to it, right? 00:51.570 --> 00:54.540 Or this name is not defined in an entity, right? 00:54.840 --> 01:00.000 Similarly, if you're considered this one right, since this is coming from here. 01:00.120 --> 01:04.430 OK, so this is also an undefined name that we have in our design. 01:04.830 --> 01:07.620 This one is also undefined, right? 01:07.980 --> 01:09.910 This one is also undefined, right? 01:10.200 --> 01:11.650 Rest of the nets are defined. 01:11.670 --> 01:17.700 So if you calculate that we have this one as the first undefined define in our design. 01:18.180 --> 01:20.870 This one represents the second and define it. 01:20.880 --> 01:23.730 And then this one represented to run the finder, right? 01:24.090 --> 01:27.960 So to define such undefined net right, we use signals, right? 01:28.410 --> 01:32.930 So let's see how we use a signal to define this and implement this system. 01:33.000 --> 01:33.200 Right. 01:33.210 --> 01:36.540 So our system consists of three input E, B and C. 01:36.960 --> 01:40.340 OK, then we have two output summary carrier. 01:40.340 --> 01:40.710 OK, right. 01:40.710 --> 01:41.760 So we'll go ahead. 01:41.820 --> 01:46.770 We will use the C project, which we utilize for development off and hopping, right? 01:46.770 --> 01:48.810 So we'll just be closing our simulation. 01:48.900 --> 01:51.990 We go ahead and select the design to target. 01:52.310 --> 01:53.540 Right, right click. 01:53.760 --> 01:58.770 And then you could add a source from here, or you could just click on this plus button, right? 01:59.070 --> 02:02.510 So this will take us to new source who is out, right? 02:02.520 --> 02:05.150 And here we will be adding the new source. 02:05.160 --> 02:07.650 Let it just name this as folder. 02:08.160 --> 02:10.070 Right click OK and then hit finish. 02:10.950 --> 02:16.470 Now here we have three input groups the each of say a single bit, so we could use comma and declare 02:16.500 --> 02:17.920 all of them went straight. 02:18.630 --> 02:24.010 So e b and then seen rates of this represent three input. 02:24.660 --> 02:30.120 That action is input and say this single bit rate, then we have two output for each of these single 02:30.330 --> 02:32.770 to s see out right. 02:32.790 --> 02:34.410 That addiction will be output. 02:34.410 --> 02:35.250 Write this again. 02:35.250 --> 02:36.470 Have a say a single bit. 02:36.940 --> 02:41.760 OK, now this will automatically create the template for a state. 02:41.910 --> 02:45.540 Now you'll be finding we have a dual source code inside design source. 02:45.730 --> 02:45.960 Right. 02:45.960 --> 02:48.980 So that which we used in the previous example. 02:48.990 --> 02:51.110 And now we plan to work with Solaris. 02:51.150 --> 02:57.030 So whenever you have a multiple source, see that you correctly choose the top movie, so top model 02:57.030 --> 03:04.650 will be chosen depending on which source code you want to use for this specific demonstration. 03:04.860 --> 03:07.230 We plan to work with Falak, right? 03:07.410 --> 03:11.400 So the all the steps that you see on the floor navigate. 03:11.730 --> 03:18.600 So we have a simulation synthesis, implementation and Instagram, and even all of these steps will 03:18.600 --> 03:24.620 be performing will be performed on a module which have this three chip neighbor into it, right? 03:24.630 --> 03:29.340 And that basically represent that that specific source code is the top rate. 03:29.670 --> 03:31.500 Now here we want to work with the collider. 03:31.530 --> 03:37.350 So see that as soon as you add multiple source, you correctly choose your top model right to the source, 03:37.350 --> 03:44.700 which is top model will be the one which will be chosen for all the steps that you perform in that FPGA 03:44.700 --> 03:45.090 design. 03:45.390 --> 03:45.690 Right? 03:45.900 --> 03:52.350 So we'll be right click on the collider and then we will be setting it desktop right now. 03:52.350 --> 03:56.580 All the processes that you see in and you navigate that will be on full, right? 03:56.610 --> 03:58.680 So this is the first thing that we do again. 03:58.680 --> 04:03.470 We want to perform a simulation on the collider only, so we go through simulation sources. 04:03.470 --> 04:06.690 So the heroes who you point to sources are there. 04:06.690 --> 04:11.190 We have incorporated, we have a folder and now we want to perform a simulation on the collider. 04:11.190 --> 04:14.070 So we just right click and set it to a stop, right? 04:15.030 --> 04:21.150 So these are the two necessary thing that you need to do when you have multiple sources present in your 04:21.150 --> 04:21.580 project. 04:21.600 --> 04:26.250 Right now we go to a folder, OK, and will perform the necessary modification. 04:26.280 --> 04:29.940 Right now, the expression for some, right? 04:29.940 --> 04:35.430 So if you go ahead, the first logic gate that you have over here is all right. 04:35.430 --> 04:40.080 So let me just declare this as the one. 04:40.180 --> 04:40.440 Right. 04:40.440 --> 04:41.820 So this is a temporary one. 04:42.380 --> 04:48.470 Then let it just declare the 62 and then this thing right now, doesn't it have a size of single? 04:48.840 --> 04:51.180 So all of these databases of single bit? 04:51.510 --> 04:56.010 So we go ahead and we know that undefined net could be declared with the help of Signal, right? 04:56.010 --> 04:57.780 So we could give our signal. 04:57.810 --> 05:00.000 All of this need to have a single size right. 05:00.000 --> 05:01.620 So have the CMC. 05:01.620 --> 05:07.710 So we go ahead and we add D1 Juanma D2 comma. 05:08.520 --> 05:13.800 So whenever you have a multiple net of, say, single digit code, again use a comma similar to what 05:13.800 --> 05:15.000 we did with a few calls. 05:15.840 --> 05:17.040 Then we define the date. 05:17.370 --> 05:19.980 So standard and whole logic, right? 05:20.220 --> 05:24.400 And to initialize the net, we could just use schooland equals two. 05:24.430 --> 05:27.840 OK, and then we add in a single code zero. 05:27.850 --> 05:32.670 So this will declare three temporary variable of, say, single bit. 05:32.820 --> 05:37.300 OK, then we proceed or implementing the circuit. 05:37.380 --> 05:42.420 Right now, you clearly see D1 is equal to E x RB, right? 05:42.420 --> 05:46.490 So we go ahead and we write divide equals two. 05:46.500 --> 05:49.170 Swaggy equals two will be signal assignment. 05:49.610 --> 05:49.860 Right. 05:49.870 --> 05:53.340 So this will request to e expr be right. 05:53.340 --> 05:55.380 This complete our first block. 05:55.800 --> 05:57.090 Then we have. 05:57.420 --> 06:00.260 So if you can observe design, right? 06:00.600 --> 06:04.170 So this represented A. Do it week was to n right. 06:04.170 --> 06:09.520 So this is the second thing that we will vary will be E and B. 06:09.540 --> 06:15.090 So we completed this to get right next to and that we have is this one. 06:15.330 --> 06:22.080 So if you consider the output of this greatest sum again in Buddhist D1 and C in right, so some is 06:22.080 --> 06:26.250 equals to some is still OK even. 06:27.180 --> 06:34.280 XOR with C in right, so we'll just be adding this expression, so this completes the logic for us. 06:34.890 --> 06:41.190 Then if you can see three three is equals two to one and see right three. 06:42.770 --> 06:44.000 Easy to. 06:45.270 --> 06:52.560 The U.N. had seen this week since last July that we have in our design, is this audit right? 06:52.800 --> 06:58.340 And who's out this carry out Sicario this week equals two three three or did great. 06:58.410 --> 07:00.960 So we go ahead and we add seal. 07:01.470 --> 07:01.770 Right? 07:01.770 --> 07:04.020 So SEAL will be close to. 07:05.090 --> 07:05.540 You do. 07:06.200 --> 07:06.560 OK. 07:07.080 --> 07:12.680 All right, so this completes our entire circuit, right? 07:12.830 --> 07:19.400 So this is how we implement the circuit with our data flow, Morgan State and here we also and discern 07:19.400 --> 07:20.960 how we declared an undefined. 07:21.230 --> 07:21.530 Right. 07:22.010 --> 07:22.760 Now we go ahead. 07:22.970 --> 07:25.850 First, we see you are followed by basic controls, OK? 07:25.860 --> 07:30.160 And then we go ahead and open an ideal schematic. 07:30.440 --> 07:35.130 So that is the first process that we do until we complete our source code. 07:35.150 --> 07:35.420 Right. 07:35.990 --> 07:40.480 So we go to our ideal analysis and we choose schematic. 07:40.710 --> 07:45.680 So this will open up the schematic and this should be matching with the schematic that you have utilized 07:45.680 --> 07:49.420 for implementation of your system method of modeling. 07:49.640 --> 07:49.880 Right. 07:50.240 --> 07:55.670 So some basically have SRB and then finally starting that seed, right? 07:55.850 --> 08:01.100 So if you observe X or B whose output is further XOR with scene, right? 08:01.100 --> 08:09.380 And this gives us some OK as they'll carry out as equals to A and B, so EIB, this is that output. 08:09.950 --> 08:15.500 Similarly, B and C, so here you have your XOR output, right? 08:15.510 --> 08:16.940 And the C that output. 08:17.240 --> 08:18.730 OK, so these are the two I get. 08:18.740 --> 08:21.170 And then finally, they are together to get C. 08:21.170 --> 08:21.590 All right. 08:21.590 --> 08:25.790 So this exactly matches to what you have over here, right? 08:26.240 --> 08:29.600 So we go ahead and try to perform a simulation, right? 08:29.870 --> 08:31.550 So we select run simulation. 08:31.550 --> 08:35.990 We already set our folder as a top model in the simulation source also. 08:36.200 --> 08:38.630 So we click on behavioral simulation, right? 08:38.690 --> 08:43.160 Again, we need to apply a manual stimulus to A, B and C. 08:43.160 --> 08:49.550 And since we haven't written any test bench, right, so we go, Hey, we have a b and C, which are 08:49.550 --> 08:52.400 the input to our design, right? 08:52.400 --> 08:57.380 So we select both clock one and zero will be using a different bit rates. 08:57.380 --> 09:03.290 So far, a b that is a good use would lock one two zero and here we will be using a period of three 09:03.290 --> 09:05.780 hundred nanosecond and four C in. 09:07.980 --> 09:16.550 Get one to zero and let it just choose the period of 509 rates, the ones you set up the clock for all 09:17.140 --> 09:20.070 there, they just go ahead and click on this brown button. 09:20.070 --> 09:29.490 Right now, if you also see when all of the inputs are high and ISO is also high, BS all sciences. 09:29.490 --> 09:32.010 Also, in that case, some incredible should be high. 09:32.280 --> 09:33.930 That is what is happening over here. 09:34.140 --> 09:40.820 If you observe this scenario so easy to these high seas, high rate, so we have too high, so our scouts 09:40.820 --> 09:42.960 should be high, some should be zero, right? 09:42.960 --> 09:48.620 So this is also matching to an expected reserve when we have all of them at zero. 09:48.630 --> 09:51.480 So I wrote something sea out should be easy, right? 09:51.750 --> 09:58.920 So I carry out our storm and carry on, but are working at expected and that is also working as expected.