----------------------Design Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_4 is
    Port ( clk,wr : in STD_LOGIC;
      oe : in std_logic;
     din : in std_logic_vector(3 downto 0);
     dout : out std_logic_Vector(3 downto 0);
     addr : in std_logic_Vector(3 downto 0)  
    );
end ram_4;
 
architecture Behavioral of ram_4 is
 
type ram_type is array (0 to 2047) of std_logic_vector(3 downto 0);
signal ram:ram_type;
signal temp : std_logic_vector(3 downto 0);
begin
 
process(clk)
begin
if(rising_edge(clk)) then
  if(wr = '1') then
    ram(to_integer(unsigned(addr))) <= din;
  else
    temp <=  ram(to_integer(unsigned(addr)));
  end if;
end if;
 
end process;
 
dout <= temp when ( oe = '1' and wr = '0' ) else (others => 'Z');
 
end Behavioral;

---------------------Testbench Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
 
entity ram_tb is
end ram_tb;
 
architecture Behavioral of ram_tb is
 
component ram_4 is
    Port ( clk,wr : in STD_LOGIC;
      oe : in std_logic;
     din : in std_logic_vector(3 downto 0);
     dout : out std_logic_Vector(3 downto 0);
     addr : in std_logic_Vector(3 downto 0)  
    );
end component;
 
 
 
 
signal     clk,wr :    STD_LOGIC := '0';
signal      oe :   std_logic := '0';
signal     din :   std_logic_vector(3 downto 0) := "0000";
signal     dout :  std_logic_Vector(3 downto 0);
signal     addr :  std_logic_Vector(3 downto 0) := "0000"; 
begin
 
T1 : ram_4 port map (clk => clk, wr => wr, oe => oe, din => din, dout => dout, addr => addr);
 
clk_gen: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
 
stimuli: process 
begin
 
--------Data Write
wr <= '1';
addr <= "0000";
din <= "0000";
wait for 10 ns;

wr <= '1';
addr <= "0001";
din <= "0101";
wait for 10 ns;

wr <= '1';
addr <= "0010";
din <= "1010";
wait for 10 ns;

wr <= '1';
addr <= "0011";
din <= "1111";
wait for 10 ns;
----------------------------
addr <= "0000";
oe   <= '0';
wr   <= '0';
din  <= "0000";
wait for 10 ns;
 
----------------Reading data from RAM
 
wr <= '0';
oe <= '1';
addr <= "0000";
wait for 20 ns;
 
 
wr <= '0';
oe <= '1';
addr <= "0001";
wait for 20 ns;
 
 
wr <= '0';
oe <= '1';
addr <= "0010";
wait for 20 ns;
 
wr <= '0';
oe <= '1';
addr <= "0011";
wait for 20 ns;
 
end process;
 
end Behavioral;

--------------------Constraint File

set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 10.00  [get_ports { clk }];


set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { din[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { din[1] }]; #IO_L24P_T3_34 Sch=sw[1]
set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { din[2] }]; #IO_L4N_T0_34 Sch=sw[2]
set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { din[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]


set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { addr[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { addr[1] }]; #IO_L24N_T3_34 Sch=btn[1]
set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { addr[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { addr[3] }]; #IO_L7P_T1_34 Sch=btn[3]

set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { dout[0] }]; #IO_L23P_T3_35 Sch=led[0]
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { dout[1] }]; #IO_L23N_T3_35 Sch=led[1]
set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { dout[2] }]; #IO_0_35 Sch=led[2]
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { dout[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]

set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33     } [get_ports { wr }]; #IO_L10P_T1_34 Sch=jc_p[1]   			 
set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33     } [get_ports { oe }]; #IO_L10N_T1_34 Sch=jc_n[1]