WEBVTT 00:00.060 --> 00:02.080 So now let's try to perform a simulation. 00:02.340 --> 00:07.620 So for that, we'll be adding with this feature to select the simulation source, go ahead and click 00:07.620 --> 00:10.320 on this plus button and create a simulation. 00:10.320 --> 00:12.420 So click OK, create play. 00:12.420 --> 00:15.050 And we'll just be naming this as RAM, right? 00:15.070 --> 00:20.340 And we'll finish notice which schools do not consist of any input and output pool. 00:20.340 --> 00:21.480 So we'll just be clicking. 00:21.820 --> 00:22.910 OK, great. 00:23.220 --> 00:29.430 Again, we need to go to a curriculum page where we have this Panchkula relating to will just be copying 00:29.430 --> 00:30.350 an entire quote. 00:31.320 --> 00:37.770 And then adding it into the TV, which has been added over here, right, so the simulation this will 00:37.770 --> 00:42.270 be finding along with the design code, you also have a test which will just open. 00:42.270 --> 00:48.420 It will delete everything, the complete that has been created by default and then flag the code that 00:48.420 --> 00:50.310 we copied from the cubicle. 00:50.700 --> 00:50.940 Right. 00:51.270 --> 00:57.060 So as soon as you do this, you'll be finding the RAV4, which represent our designed to automatically 00:57.060 --> 01:04.050 become a daughter model and drama school TV, which is our testing school and its name will serve as 01:04.080 --> 01:04.800 the pattern. 01:05.200 --> 01:07.710 OK, if this happens, we are ready to proceed. 01:07.740 --> 01:08.010 Great. 01:08.850 --> 01:14.470 Then we proceed to the next step where we click run simulation and behavioural simulation. 01:14.510 --> 01:20.530 OK, so the code that we have written it just in reading a few random number, applying it onto a random 01:20.550 --> 01:23.310 memory and taking the CMB down. 01:23.600 --> 01:25.590 So if you do, this time plays a code. 01:26.950 --> 01:31.770 What we are doing is, of course, we are performing a right operation, so here you could see right 01:31.770 --> 01:32.600 signal is high. 01:33.090 --> 01:33.390 OK. 01:33.630 --> 01:36.800 And then we are making raids. 01:37.380 --> 01:43.140 So here we are basically reading the data and I'll put in a village also high in that specific instance. 01:43.350 --> 01:45.630 So the Leader API ranking is zero five. 01:46.620 --> 01:46.940 Right? 01:47.220 --> 01:55.560 And from this block onwards, we are reading the data and you see see you fly the data that we have 01:55.890 --> 01:56.240 written. 01:56.360 --> 01:56.690 Right. 01:56.970 --> 02:06.000 So this completes the functional verification of OK, so it is behaving correctly, then the next step 02:06.000 --> 02:08.220 is to perform a synthesis, right? 02:08.220 --> 02:14.000 So in an ideal analysis, you could analyze the component which have been invoked while you I still 02:14.080 --> 02:14.250 could. 02:14.580 --> 02:19.520 We just go ahead and analyze the schematic, analyze the schematic for an ideal. 02:20.830 --> 02:26.080 OK, so you can clearly see the idea of them being involved in the series of raids this too far. 02:27.190 --> 02:33.960 Reading back to Detroit, we utilize it for that reason, we have an IPL regular here, right? 02:34.360 --> 02:38.530 So this is the schematic, then we will be proceeding for. 02:39.460 --> 02:44.770 Performing synthesis, so we'll just go and click on grand synthesis. 02:46.340 --> 02:51.590 So as soon as you are saying this, this is complete, it will just go away and when a synthesis did 02:51.590 --> 02:51.830 say. 02:53.410 --> 02:58.060 OK, and then we will just be performing a. 02:59.260 --> 03:02.080 Remember that before proceeding for an implementation. 03:02.380 --> 03:05.950 We need to specify the port they we want to connect our. 03:07.280 --> 03:12.260 I that we have in our design, right, so what we're going to do is we'll just go to a small step, 03:12.800 --> 03:17.030 OK, in a screen folder, we'll just be right clicking and outsource. 03:17.150 --> 03:21.140 So this will give us an option to add a new constraint. 03:21.230 --> 03:27.260 OK, we'll just be naming this stop and we'll hit right now if you just go away. 03:27.300 --> 03:29.040 And then they stopped or next. 03:29.690 --> 03:30.520 OK, who year? 03:30.520 --> 03:32.950 We do not have anything so inaccurate can be. 03:32.960 --> 03:36.250 The third thing which is mentioned is the cancer gene. 03:36.950 --> 03:42.950 So we'll just be copying this and we'll be adding it all right to this complete on. 03:45.050 --> 03:50.510 And then what are we going to do this so to perform about poverty analysis? 03:51.080 --> 03:58.130 We'll just reload our synthesis to say, OK, and what we are planning here is we will be adopting one 03:58.130 --> 03:59.550 of an implementation strategy. 03:59.570 --> 04:05.570 So you already know that synthesis will transform our actual goal into the FPGA primitives, right? 04:05.960 --> 04:11.060 So as soon as you perform a synthesis now, as soon as we are constrained, you could see that synthesis 04:11.060 --> 04:11.960 out of the right. 04:12.230 --> 04:19.490 So good idea would be that you again perform a synthesis one more time with an updated Consti so that 04:19.490 --> 04:28.460 when we perform and follow me coming there, it could take the related data for computing. 04:28.460 --> 04:35.540 The dynamic power that you are consuming will just be performing a synthesis one more time off the addition 04:35.540 --> 04:36.260 of constraint. 04:37.870 --> 04:43.240 So our synthesis is completed again, they now will go ahead and will try to measure the power. 04:43.270 --> 04:48.060 So you do see you have an option as well, put power over here. 04:48.070 --> 04:50.620 So we'll just be going ahead and report power. 04:51.490 --> 04:56.830 And they're the only important parameter that you want to analyze is. 04:57.850 --> 04:59.350 Does switching and switching. 04:59.620 --> 05:04.000 You could see you have a gene clock, so here you should have a valid. 05:05.370 --> 05:11.130 Leading site, so here we are considering the nanosecond clock, and we're just here to right, so this 05:11.130 --> 05:15.710 will automatically compute the bomb before it's so innocent. 05:15.720 --> 05:16.510 Is this OK? 05:16.530 --> 05:23.790 You could see the clock is consuming 50 percent of of power, whereas I are consuming 38 percent of 05:23.790 --> 05:24.370 total power. 05:24.390 --> 05:25.170 What are you going to do? 05:25.170 --> 05:32.280 It will just be keeping the snapshot of this because as we adopt an implementation strategy, specifically 05:32.280 --> 05:36.360 an optimization strategy, we could easily compare the difference rate. 05:36.840 --> 05:42.600 So once you complete the synthesis, the next step now you already know that your design has been transformed 05:42.600 --> 05:47.010 to something that you understand, which is different than in the good. 05:47.130 --> 05:52.800 That will always be the go around simulation and at least perform a functional simulation. 05:52.810 --> 05:54.690 So that is what we to do. 05:55.410 --> 05:57.630 And this will take the same test bench. 05:57.810 --> 06:02.940 So we do not need to write the different code for this right and will again be observing whether we 06:02.940 --> 06:05.070 are getting the same result or not. 06:05.180 --> 06:05.700 Right, so. 06:07.040 --> 06:10.550 Just be going ahead and then we will be analyzing. 06:10.850 --> 06:13.910 So 05 here and then here. 06:15.350 --> 06:23.150 So here we are, getting zero five affinity, right, so this is also matching with the heat that we 06:23.150 --> 06:24.620 are getting in the previous state. 06:25.020 --> 06:26.600 And what are we going to do next? 06:26.960 --> 06:30.020 So we will just be closing this simulation Typekit. 06:31.430 --> 06:37.370 So usually what happens is if your data is not matching in the case of when you perform a synthesis, 06:37.790 --> 06:44.060 so basically you try to delete your stimulus application for you. 06:45.050 --> 06:50.720 Nanosecond, so usually one nanosecond is the time you have for the global reset, right? 06:50.720 --> 06:58.190 So what you going to do is you do not apply any stimulus for first nanosecond and after a nanosecond, 06:58.190 --> 07:03.710 you start applying the stimulus that will in most cases, correct if you are getting any mismatch right. 07:04.550 --> 07:08.620 So since this is completed, we already specify a constraint. 07:08.630 --> 07:09.080 We're here. 07:09.180 --> 07:12.350 OK, so the next step is to perform an implementation. 07:12.350 --> 07:18.770 So depending on the food that we specify a specific location on an FPGA dice choosing where ideologic 07:18.770 --> 07:25.130 will replace OK, and that strongly depend on the boots that we specify in a constrained play, right, 07:25.130 --> 07:27.500 so will allow the implementation to complete. 07:28.130 --> 07:28.460 OK. 07:29.800 --> 07:31.590 And the next. 07:31.760 --> 07:36.140 So now watching this is complete, the next step is to perform an implementation. 07:36.670 --> 07:38.380 So implementation will basically. 07:39.300 --> 07:44.580 Choose the specific location on an FPGA type where I will be placing ideologic right now, here are 07:44.580 --> 07:50.320 a nice to optimize our design for our requirements. 07:51.240 --> 07:54.480 So here we want to reduce our dynamic power, right? 07:54.480 --> 07:59.030 And that could be done easily by utilizing one of an implementation strategy, right? 07:59.070 --> 08:02.790 So we'll go to the setting before performing an implementation. 08:03.600 --> 08:10.740 And then in an implementation, you could actually see that you have an option to opt the power, right? 08:10.740 --> 08:14.190 So we'll just be taking that option and then we'll be proceed. 08:15.450 --> 08:22.760 OK, so here you have power up, design will just be enabling this will click apply and then hit. 08:23.670 --> 08:28.080 So with this modification will be going to perform an implementation, right? 08:28.290 --> 08:31.590 Now here we have adopted one of an implementation strategy. 08:32.100 --> 08:37.470 So this will modify our design, such as to meet the requirement that we specify. 08:37.470 --> 08:43.830 Hence, it becomes mandatory that we perform a kind of functional simulation after the implementation 08:43.830 --> 08:44.890 is complete. 08:45.120 --> 08:45.350 Right. 08:46.380 --> 08:47.700 Again, implementation. 08:48.090 --> 08:54.060 Choose this specific location on an average day, depending on the bent that you have specified. 08:54.280 --> 08:59.550 So specifying a constraint before performing an implementation fee is a very crucial. 09:01.160 --> 09:02.930 So our implementation is completed. 09:03.050 --> 09:07.640 Now what we're going to do is we will be going to open implementation design. 09:08.090 --> 09:08.390 OK. 09:08.510 --> 09:11.000 And here we have a report, our optional. 09:11.150 --> 09:16.400 So in the previous case, you could clearly see the power that we are consuming is 53 percent with the 09:16.400 --> 09:19.190 clock and with an eye, we are getting 38 percent right. 09:19.580 --> 09:25.010 So it will go away and we already adopted the public of strategy for our design. 09:25.460 --> 09:30.610 Just be reporting a power after an implementation rate, so let it just go away again. 09:30.620 --> 09:36.240 Only thing that you need to check is whether constraint clock is correctly specified with the Respect 09:36.380 --> 09:37.420 specification, right? 09:37.430 --> 09:45.440 So here also we have a clock of 10 nanosecond and now you could see that we able to reduce the dynamic 09:45.440 --> 09:45.950 locking. 09:46.130 --> 09:46.490 OK. 09:47.690 --> 09:49.640 Two, forty three percent rate. 09:50.450 --> 09:57.410 So the power up helps to reduce the dynamic sucking dynamic. 09:58.630 --> 10:01.360 Power dissipation at least up to 30 percent. 10:01.570 --> 10:03.460 So that is the maximum range that we get. 10:03.790 --> 10:08.560 But with this simple modification, you could clearly see that we will to reduce the dynamic locking. 10:08.560 --> 10:12.910 In fact, aisle utilization has also increased. 10:13.630 --> 10:14.050 So. 10:15.370 --> 10:22.390 But you could clearly see that with an implementation strategies, you could control the dynamic locking. 10:22.390 --> 10:24.280 In fact, this is a very simple example. 10:24.610 --> 10:28.630 We won't be able to found of the much difference between good reading. 10:28.870 --> 10:34.700 But as you build up a complex example, consuming a lot of resources and a good amount of power. 10:34.720 --> 10:41.140 So there this kind of strategies are very useful so that this modification and implementation in Texas 10:41.140 --> 10:42.310 will will again go ahead. 10:42.570 --> 10:46.410 Tour and simulation are you able to see these options are also enabled, right? 10:46.410 --> 10:50.680 So will just be performing the implementation functional simulation, right? 10:50.680 --> 10:54.070 So this will be the post implementation functional simulation. 10:54.280 --> 11:01.830 Again, we do not require to specify, and it has been the theme that quote could be used for verification 11:01.840 --> 11:02.170 here. 11:02.220 --> 11:02.950 Odds, right? 11:03.490 --> 11:04.210 Yes, go ahead. 11:04.240 --> 11:08.590 And you could clearly see 05 E.F. and then 05. 11:08.800 --> 11:09.000 Right. 11:09.070 --> 11:12.250 So we are receiving the same data and we are speaking right. 11:12.490 --> 11:15.040 So we completely delay implementation. 11:15.040 --> 11:20.600 Also last step is to perform generation of a stream, so we'll just click on indeed, midstream. 11:21.060 --> 11:21.310 Okay. 11:21.520 --> 11:27.430 So this will automatically create a big fight for us, which will be utilized for our programming on 11:27.430 --> 11:28.030 FPGA. 11:28.030 --> 11:36.250 And then we could either debug our design or we could verify the operation of our system on two and 11:36.250 --> 11:37.070 Heidi, right? 11:38.750 --> 11:40.670 So I presume initially successful. 11:40.760 --> 11:43.690 You just go ahead and click on open hardware manager. 11:43.730 --> 11:48.200 OK, then we just need to click on open target or to. 11:48.450 --> 11:52.160 So this will automatically show the world that you have connected to your PC. 11:52.490 --> 11:54.910 Then you just need to program next page. 11:54.980 --> 11:55.280 Right? 11:55.460 --> 12:03.680 So this completes an entire process, OK, that we follow for the implementation of the system on an 12:03.680 --> 12:04.400 SPG, right? 12:04.400 --> 12:11.100 So we specify the source, 60W text based source, or it could be a schematic based source. 12:11.160 --> 12:14.210 OK, then we perform the functional simulation. 12:14.240 --> 12:21.230 OK, then we perform a synthesis implementation and finally generating a bitstream which would be used 12:21.230 --> 12:22.640 to program an FPGA.