Traditionally, gated clocks in ASIC designs are a common way to reduce power consumption in systems. By gating the clock, whole sets of registers can be kept from transitioning when not needed.

Fig. 1: Gating a clock with an AND gate

In Fig. 1, when the "gate" signal is set to a low condition, the registers are all turned off and are not drawing dynamic power.

This type of coding style does not always port well to FPGAs. This is because FPGAs have advanced dedicated clock resources that are designed to set the timing of the clock structures to an optimal setting, avoiding clock skew. Putting a gate in the middle of this structure can interfere with those resources. In addition, those clock resources are not unlimited, so having many different gated clocks can cause problems in an FPGA design.

Fig. 2: LUT inside the clocking structure

One way to get around these problems is to rewrite the RTL code to remove the gates. However this involves a lot of work, and in many cases when the design is being prototyped in FPGAs, the RTL is not allowed to be changed. Another way to fix this is to allow your synthesis tool to convert those gates so that the clock will drive the register clock pin directly and the gating logic will go to the clock enable pin. Vivado Synthesis does support this behavior.

Fig. 3: Same circuit with the gated clocks converted.

It should be noted for designers that doing this conversion helps the tool to use the dedicated clocking resource, but it also now uses different clock enables. This will mean more control sets in your design which can also have other effects.

Basic gates

One of the more common forms of gated clocks are clocks gated by basic gates (for example, AND gates).

Example RTL code:

assign my_clk = clk1 & gate1 & gate2;

This gates the clock with two different enables and the elaborated view looks like the following:

Fig. 5: Clock gating with AND gates

When synthesized with gated clock conversion on, and either gated_clock_conversion set to auto with a clock period on clk1, or the GATED_CLOCK attribute set on clk1, the tool will connect the clk1 signal to the C input of the register and the gate1 and gate2 signals into the CE input of the flop.

Fig. 6: Previous circuit, post Synthesis

Conversion of OR gates will also work.

Fig. 7 : Using OR gates in the clock circuit

The above circuit will get converted to the following:

Fig. 8: OR gate conversion

Vivado Synthesis can also convert more complex gates than ANDs and ORs.

Registered gates

Vivado can also convert gates that are registered.

For example, the coding style below will create a register that gets used as a clock by another register:

always@(posedge clk)
     reg_clk <= clk_in;
always@(posedge reg_clk)
     out1 <= in1;

If there is an appropriate constraint on the first clk signal, the tool be able to convert this type of gate as well.

For example :

create_clock -period 5 [get_ports clk]

Fig. 9: Elaborated view of a register used as a clock

This will get converted to the following:

Fig. 10: A register gate after being converted