WEBVTT 00:00.060 --> 00:05.460 So let us try to understand what are the different options that we get with the synthesis setting as 00:05.460 --> 00:10.350 well as in the next really will be understanding the different strategies that we get with an implementation 00:10.350 --> 00:14.490 starting before proceeding to understand the complete design, right? 00:14.790 --> 00:16.870 So to go to a synthesis setting. 00:16.890 --> 00:22.450 You just need to go either sitting over here or sitting over here. 00:22.470 --> 00:24.930 OK, but the option would work in a similar fashion. 00:25.410 --> 00:29.360 You'd just be clicking on setting and we are targeting a synthesis state. 00:29.370 --> 00:38.700 So when you go to synthesis now, you could see that you have a series of strategies related to the 00:38.700 --> 00:39.450 synthesis, right? 00:39.450 --> 00:42.580 So you could perform any optimization. 00:42.600 --> 00:47.760 You could also optimize optimize store performance. 00:47.790 --> 00:51.630 OK, and then you also have a runtime optimization, right? 00:51.630 --> 00:54.330 So there's a series of strategies which can be adopted. 00:54.660 --> 01:00.330 The more information on this could be easily found out on the reference manual that we have for and 01:00.330 --> 01:00.990 we like, right? 01:01.380 --> 01:07.470 Some of the common strategies that we frequently utilize is the gated clock conversion rate. 01:07.470 --> 01:14.190 So you could see the dynamic power by enabling the delegated lock conversion rate to what that means 01:14.190 --> 01:15.600 is listen to you. 01:15.600 --> 01:21.390 Your device consists of many such blocks in your system, right? 01:21.420 --> 01:28.100 So what this means is we are basically performing an ending between clock and the gating signal. 01:28.110 --> 01:34.590 And then when the gating signal is high, only at that instance, we are sending the clock signal to 01:34.590 --> 01:36.380 both the registered or higher rate. 01:36.390 --> 01:42.570 So these are simple d flip flop that we have and what we are doing is the clock that is going to boot. 01:42.570 --> 01:45.570 The register is and deal with the gating rate. 01:45.960 --> 01:50.820 So we have a gate in between the locking it out, right? 01:50.820 --> 01:58.150 So this is not a good practice when we consider an FPGA because FPGA atop the specific lines for delivering 01:58.150 --> 02:00.090 the clock signal from a plot of three. 02:00.720 --> 02:09.120 So if you have many such blocks at present and you are designed to looking into each and every block 02:09.120 --> 02:12.750 and then a window and gate is a bit difficult task, right? 02:12.750 --> 02:14.430 And it is also a time consuming. 02:14.700 --> 02:22.320 Instead, what you could do is so you could just enable a locking gated to blocking conversion and that 02:22.320 --> 02:24.510 will automatically handle this scenario, right? 02:24.510 --> 02:29.460 So first, we'll just be understanding how this design will be transformed to a primitive state for 02:29.460 --> 02:30.480 this to register. 02:30.590 --> 02:37.680 So when we perform a synthesis, this will be giving us NAFTA, OK, which is basically deeply flawed. 02:38.430 --> 02:38.810 OK? 02:39.090 --> 02:46.260 With the positive edge of the area, there do exist a different kind of a deeply flawed, severe utilizing 02:46.260 --> 02:51.480 FTA, which is deeply flawed with blocking able and synchronous research. 02:51.510 --> 02:51.810 Right. 02:52.350 --> 02:59.160 So we have put the primitives been applied over here and for an engaged will be utilizing LTE to right 02:59.190 --> 03:03.960 because we have simple two inputs, so we are utilizing energy to create. 03:05.070 --> 03:11.190 Now we have many such block present in our design, right, and foreign input and output. 03:11.460 --> 03:15.900 We basically I and I both and so here you could see to I booked an ad. 03:16.440 --> 03:19.770 So we have presence of many such blocks in our design. 03:20.100 --> 03:26.080 Now, once we enable, if you go to a setting and once we enable this gated conversion. 03:26.100 --> 03:26.460 OK. 03:27.510 --> 03:35.580 If you just select and on over here, OK, in that case, what will happen is now the easiest ideas. 03:35.610 --> 03:39.510 Now we want to apply the clock whenever gate is high, right? 03:39.840 --> 03:42.630 So we could connect this gate signal to a clock enable. 03:42.630 --> 03:43.830 And that is the strategy. 03:43.830 --> 03:48.120 What is adopted, one to enable a greater clock conversion rate. 03:48.120 --> 03:53.670 So as soon as you enable a beautiful conversion, you could clearly see the gate signal OK is being 03:53.670 --> 03:56.370 applied to the clock enable of FDI. 03:56.430 --> 04:03.390 OK, so it has been acting as the clock enabled for both the register and thereby we are preventing 04:03.600 --> 04:07.620 the presence of any logical gate. 04:07.650 --> 04:13.080 OK, between the clock rate and that basically seems a good amount of power. 04:13.110 --> 04:13.410 Right. 04:13.800 --> 04:20.000 So this is the strategy that is helping us easily optimize our entire system, right? 04:20.010 --> 04:27.170 So we do not need to look for each and every part of our design for the presence of this specific block, 04:27.180 --> 04:27.550 OK? 04:27.570 --> 04:32.870 We could just enable the gated block conversion and then we able to get an optimized circuit rate. 04:32.880 --> 04:36.360 So more of this could be more similar. 04:36.360 --> 04:38.400 Example could be if you have a multiple gate. 04:38.810 --> 04:45.690 OK, bridging between the part of your clock in that is also one to enable the gateway clock and religion 04:45.690 --> 04:46.320 you could see. 04:46.650 --> 04:51.930 OK, they'll be able to automatically choose what is the signal that should be out at two o'clock? 04:51.930 --> 04:56.900 Enable and clock is kept on the single independent clock light. 04:57.180 --> 04:58.110 So here you would see. 04:58.830 --> 05:07.480 We basically want to perform or we want to send the clock to the register only when gate one and gate 05:07.530 --> 05:08.820 to boot out to, right. 05:08.840 --> 05:12.950 So in this case, the good strategy will be to add a lot. 05:13.090 --> 05:19.290 OK, where we feed gate one and two and then feed this to the clock, enable rate and clipping clock 05:19.590 --> 05:20.940 on the separate lock lane. 05:21.300 --> 05:24.230 OK, and then feeding that to a clock. 05:24.270 --> 05:24.540 Right. 05:24.540 --> 05:29.190 So this you automatically get if you enable the gate clock. 05:29.190 --> 05:37.980 And much like the next strategy that we have, all that we frequently uses right to bug the number of 05:38.370 --> 05:42.120 clock before that you have in your device, right? 05:42.120 --> 05:46.830 So we have a limited amount of count which are present in each and every device. 05:46.860 --> 05:53.520 OK, so twelve is the maximum count that we have in the pool that we have selected over here, right? 05:53.790 --> 06:00.030 So if you want to keep it about, you have a level four and either subsystem. 06:00.120 --> 06:06.630 OK, so let's assume you are designing one offers up system and then someone else is designing another 06:06.900 --> 06:07.830 subsystem, right? 06:07.830 --> 06:15.030 So you are restricted to utilize the limited number of PUBG, then that could be controlled over here. 06:15.060 --> 06:22.320 Right to good specify according to a requirement above you that are allowed and then your entire design 06:22.320 --> 06:27.390 will automatically be implemented considering the account that you specify. 06:27.450 --> 06:27.720 Right. 06:28.470 --> 06:35.340 The next one that we frequently utilizes FSM right to as we build up our control, but so we frequently 06:35.820 --> 06:39.480 use the complex FSM OK to implement our control by. 06:39.510 --> 06:46.650 So in that case, there is a team you want to control, though, including used for the implementation 06:46.650 --> 06:47.220 of benefits. 06:47.220 --> 06:53.280 And Rachel, if you want to have a simple circuit, the good strategy will be to use and when encoding. 06:53.310 --> 06:57.570 But if you want and that also give us a good amount of performance, right? 06:58.440 --> 07:07.380 But that to consume a more area that's compared to the other encoding technique, right to, for example, 07:07.480 --> 07:13.680 beagley including will consume a lesser amount of memory as compared to our including excel in OneNote 07:13.680 --> 07:18.760 and goodI if you just look to how the different technique encode the street. 07:18.780 --> 07:25.710 So if you assume that we have a five state, so each bit will be saying OK for a student, one heart 07:25.770 --> 07:26.330 encoding. 07:26.340 --> 07:29.520 So since we have a five students, we require Typekit variable rate. 07:29.790 --> 07:31.770 So this leads to very simple logic. 07:31.950 --> 07:35.610 But then we are going to mean more right? 07:35.640 --> 07:42.000 And this logic is a bit faster because we do not need to perform an decoding operation over here, right? 07:42.240 --> 07:47.040 If you consider it a binary code and the Greek or both will consume less amount of money. 07:47.310 --> 07:51.010 But since we need to add a decoding logic, they are a bit slower. 07:51.180 --> 07:57.240 So depending on the requirement that you are targeting, you could choose which type of including to 07:57.240 --> 08:00.150 be adopted for your control by deficit, right? 08:00.510 --> 08:03.930 And that could be done by utilizing. 08:04.480 --> 08:09.880 The option that you get in a synthesis setting and which is FSM extraction. 08:10.100 --> 08:16.600 So these are some of the frequent techniques that we utilize in our design. 08:16.740 --> 08:16.930 Right. 08:16.930 --> 08:23.380 So the more discussion on this of more understanding of this could be done easily by going through a 08:23.380 --> 08:24.280 reference manual. 08:24.580 --> 08:24.930 OK. 08:25.810 --> 08:33.640 But some of the strategy, which give us more insight into how the synthesis setting could be adopted. 08:33.640 --> 08:39.280 So we have discovered some of the fundamental thing that we frequently do just to get an understanding 08:39.280 --> 08:46.090 of how synthesis setting would be helpful in optimizing the certain blocks present in our design.