WEBVTT 00:00.060 --> 00:03.690 So let us try to summarize an entire design for Rachel. 00:03.930 --> 00:07.920 First step is to specify our design, right? 00:07.920 --> 00:10.590 And we have a two types of design entries over here. 00:10.920 --> 00:17.400 So it could either be text base, OK, or it could be a schematic straight. 00:17.400 --> 00:21.960 So these are the two ways by which you could perform the design entry. 00:22.380 --> 00:28.440 So in the text base, you could either specify of your steel source code or very lock source code. 00:29.190 --> 00:31.800 OK, and then we have a system very lock source code. 00:31.800 --> 00:35.340 So these are the three popular language that we frequently replace. 00:35.700 --> 00:41.220 Then in the schematic based design method, here we use our block design, right? 00:41.220 --> 00:46.680 So as we progress towards an eyepiece, we will be understanding more on this right. 00:47.250 --> 00:54.420 So once I source been specified and along with this, we completed the behavior that we are intended. 00:54.690 --> 00:55.050 OK? 00:55.230 --> 01:01.320 The next step is to check whether it is operating functionally correct date and how we verify it. 01:01.680 --> 01:08.460 We basically apply a stimulus to an input and observe an output crate, and that is done by the step 01:08.460 --> 01:10.920 two, which is a behavioral simulation, right? 01:10.920 --> 01:14.880 So behavioral simulation could be divided into three categories. 01:14.880 --> 01:18.950 So it will be a pre synthesis behavioral simulation. 01:18.960 --> 01:25.200 So let's assume you haven't performed synthesis as well as implementation so that represent the first 01:25.770 --> 01:29.410 simulation where we just apply a stimulus. 01:29.430 --> 01:35.400 OK, and then also the response we are getting on initial core right that that is. 01:36.910 --> 01:43.030 PRISM, this is a behavioral simulation next one that we have is opposing this is behavior simulation 01:43.030 --> 01:50.240 right after we performers and this is the again perform a behavioral simulation because there will be 01:50.290 --> 01:52.270 the differences in the. 01:53.340 --> 01:56.750 So behavioral simulation could be divided into three categories, right? 01:56.850 --> 02:00.090 First is when we haven't performed this synthesis. 02:00.480 --> 02:00.840 OK. 02:00.870 --> 02:03.750 That is where we perform a function of verification. 02:03.750 --> 02:10.080 So just we have performed and implementation of our system will give it the source code. 02:11.040 --> 02:14.970 So behavioral simulation could be divided into three categories, right? 02:15.000 --> 02:17.190 So we haven't performed synthesis yet. 02:17.490 --> 02:21.330 And then we are just checking whether our deal is behaving correctly. 02:21.660 --> 02:23.880 So that is the first behavioral simulation. 02:24.300 --> 02:31.290 The next one is after we performance, and this is we again perform our verification of our system functionality. 02:31.290 --> 02:33.510 That is the second behavioral simulation. 02:33.510 --> 02:37.530 No, there we could also verify whether timings are also correct or not, right? 02:37.800 --> 02:40.490 And the third is when we perform an implementation, right? 02:41.640 --> 02:47.400 So these are the three different kind of behavioral simulation that will be performing great synthesis, 02:47.400 --> 02:56.310 transform our HDL code to something that our FPGA and this generated consist of net sensors also celebrating 02:56.310 --> 02:59.700 the primitives, which are available for a specific device family, right? 03:00.300 --> 03:06.990 Something which we could do to optimize the primitives that have been invoked by default by and we will 03:06.990 --> 03:11.400 do is to utilize the sitting state and these are the optimization strategies. 03:11.400 --> 03:17.730 So common optimization strategies include the number of bugs that you could get both genes that you 03:17.940 --> 03:20.880 could invoke in this. 03:21.210 --> 03:28.320 And the second one that we frequently utilize is the including stay low key when we have a complex surface. 03:29.280 --> 03:34.750 The third one could be whether you want to control the dynamic power distribution. 03:34.790 --> 03:37.520 OK, so adding a clock? 03:38.340 --> 03:42.570 So these are the three popular techniques that we frequently utilize in a sentence is now you would 03:42.570 --> 03:49.510 see that when we specify idea you, so HDL will be transformed to an FPGA primitives. 03:49.530 --> 03:49.860 OK. 03:50.100 --> 03:57.780 So it became mandatory to verify the functionality, whether I device or whether our system still behaves 03:57.780 --> 03:58.590 as expected. 03:58.590 --> 04:06.840 Because when we perform a behavior simulation prior to synthesis, so we consider any still go right 04:06.840 --> 04:12.810 now, still call this transform into a primitives so it becomes mandatory that you even do. 04:12.810 --> 04:19.380 If you do not apply those synthesis strategies, it becomes mandatory that you perform behavioral simulation, 04:19.390 --> 04:19.620 right? 04:19.620 --> 04:28.230 So this is the post synthesis behavioral simulation, and this could be referred as previous synthesis 04:28.230 --> 04:28.800 and present. 04:28.800 --> 04:32.850 This is basically mean that it is also pre implementation, OK? 04:33.090 --> 04:36.240 And the third category is the post implementation. 04:36.900 --> 04:37.250 OK. 04:37.950 --> 04:44.060 Then once we have our design now here, we need to specify before proceeding for an implementation, 04:44.070 --> 04:46.590 we need to specify a constraint, right? 04:46.590 --> 04:47.520 That is mandatory. 04:47.790 --> 04:52.140 So we'll be choosing, depending on the pool that we have in our source code, will be connecting it 04:52.140 --> 04:55.530 to the specific peripheral that we want to connect them. 04:55.710 --> 04:59.750 OK, and that is mainly data, because utilizing them are we? 04:59.760 --> 05:03.900 Why do we decide where the logic should be placed in an FPGA, right? 05:04.620 --> 05:08.970 So here constraint should be added monetarily. 05:09.000 --> 05:11.820 Once that is done, we will proceed to an implementation date. 05:12.870 --> 05:15.780 This will automatically do the placement. 05:16.560 --> 05:22.590 So as soon as we specify a constraint that we would all automatically choose the most suitable site, 05:22.590 --> 05:25.360 depending on the pins that we specify right here. 05:25.380 --> 05:32.640 We could also adopt some of the strategies if you are designing required certain specific constraint. 05:32.640 --> 05:39.110 OK, so these include the area constrain or timing, constrain or power constraint. 05:39.120 --> 05:46.110 OK, so we could adopt the optimization techniques OK by adopting the implementation strategies while 05:46.110 --> 05:47.700 we are performing an implementation. 05:47.700 --> 05:54.210 So this could be done by going into a setting of an implementation and choosing the specific optimization 05:54.570 --> 05:55.150 strategy. 05:55.210 --> 05:55.410 Right. 05:55.420 --> 06:01.440 So once your design is implemented again, you need to perform a behavioral simulation right to this 06:01.440 --> 06:06.980 basically representing our third behavioral simulation, which is post implementation behavior simulation. 06:06.990 --> 06:11.530 So once the implementation is done, the next step is to generate the R programming. 06:11.570 --> 06:12.270 Quite OK. 06:12.720 --> 06:17.670 And then you basically open that hardware manager to program and FPGA to the generated big fight. 06:18.090 --> 06:21.200 So after this, five steps are completed in a case. 06:21.210 --> 06:26.400 If you are required to debug a design, then we basically add the debugging technique. 06:26.430 --> 06:28.800 So this includes I'll NPI, right? 06:29.040 --> 06:35.340 So this is an entire flu that we follow for developing an application on an FPGA, right? 06:35.340 --> 06:38.590 So we'll just be summarizing here one by one. 06:38.610 --> 06:45.000 So the first step is the design entry design entry could be take space or it could also be the schematic 06:45.000 --> 06:49.380 there straight to one to specify a design with an ideal goal. 06:49.410 --> 06:52.710 We will be performing the behavioral simulation. 06:52.970 --> 06:55.970 So this represents a step, too. 06:57.080 --> 07:03.920 Again, this is basically police into behavior and simulation, then the third step is to perform synthesis, 07:03.920 --> 07:04.190 right? 07:04.190 --> 07:11.510 So this will basically transform your HDL to the primitive so give up and produce that is available 07:11.510 --> 07:17.110 for the specific device family, which you have chosen by creating a project right here. 07:17.300 --> 07:25.660 Also, you could adopt certain optimization if you required to if you have a specific constraints, 07:25.700 --> 07:29.270 OK, so you could adopt an optimization technique. 07:29.540 --> 07:32.630 So these are usually the resource optimization, right? 07:33.080 --> 07:36.350 Then as you complete your synthesis here. 07:36.350 --> 07:42.770 After this, we need to perform post synthesis behavioral. 07:43.810 --> 07:45.070 Simulation, right? 07:45.910 --> 07:54.640 So this completed step four, so once it matches to the expected returns, it once it gives us an unexpected 07:54.640 --> 07:57.200 result, the next step is to perform an implementation. 07:57.260 --> 08:02.140 Now we could adopt here also and optimization strategies. 08:02.170 --> 08:02.530 OK. 08:02.800 --> 08:09.040 If you want or you will just stick to the default optimization strategies which are available, right? 08:09.370 --> 08:15.370 So once you perform an implementation, you basically need to perform forced implementation. 08:17.090 --> 08:19.400 Behavioral simulation. 08:19.910 --> 08:23.540 So once you complete this, you go and change the bitstream. 08:24.320 --> 08:28.820 OK, so this should be followed by degeneration of a bitstream. 08:28.850 --> 08:29.150 Right? 08:29.480 --> 08:34.850 And then we could just program high rate. 08:35.150 --> 08:39.530 And if you are not getting an expected return, we proceed with head debugging, right? 08:39.530 --> 08:41.900 So we check for an error. 08:41.930 --> 08:46.370 And again, we go ahead and modify our code right. 08:46.370 --> 08:52.460 So basically, we will again be jumping from a debugging step to any deal. 08:52.780 --> 08:52.900 Right. 08:52.930 --> 08:55.670 So here will again be performing a modification. 08:55.670 --> 08:58.100 A game will be following an interest rate. 08:58.490 --> 09:02.960 So this is how we will be developing an application on an FPGA.