WEBVTT 00:00.140 --> 00:04.320 Once you complete the synthesis, no next step is to perform an implementation. 00:04.740 --> 00:10.620 Again, remember that specifying a constraint before proceeding to an implementation is mandated. 00:10.730 --> 00:13.950 They will just go ahead and click on an implementation. 00:13.950 --> 00:18.690 No, depending on the constraint that we specify, add logic will be pleased. 00:19.020 --> 00:24.930 The specific politician in an FPGA that so often we perform and implementation will be understanding 00:25.530 --> 00:31.860 their logic is straight, so we are utilizing only a single technology that you could see over here. 00:31.890 --> 00:32.120 Right? 00:32.550 --> 00:39.270 So let's analyze out of all the laughs that we have on our budget, which we are utilizing for the limitation 00:39.270 --> 00:39.990 upon the logic. 00:41.490 --> 00:43.320 So our implementation is successful. 00:43.350 --> 00:50.640 We'll just go ahead and click on open implementation to say, OK, and then we'll just be analyzing 00:50.640 --> 00:53.820 where exactly ideologic is straight. 00:54.660 --> 00:56.890 Now, if you analyze the schematic, great. 00:56.890 --> 01:00.570 So if you go to an implementation design that I didn't analyze the schematic. 01:00.780 --> 01:02.910 So you have exactly the same schematic, right? 01:02.910 --> 01:08.670 So the schematic that we have in the case of the synthesis and implementation domain, see OK. 01:08.670 --> 01:13.330 And this will be in most of the cases until unless you outline implementation strategies. 01:13.400 --> 01:20.770 OK, so if you try to use the area and that is some of the same and then you'll be finding implementation 01:20.770 --> 01:24.480 of schematic is different as compared to synthesis schematic. 01:24.480 --> 01:31.710 But if you do not apply any optimization strategy in that case, OK, your implementation schematic 01:31.710 --> 01:35.780 as well as in the systematic will be almost identical. 01:35.810 --> 01:36.090 Right. 01:36.090 --> 01:38.580 And that is what we are all talking over here, right? 01:38.980 --> 01:42.780 And now when we go to a device rate, so. 01:44.040 --> 01:54.030 If you analyze the place where we have utilized the the place where we added our logic is this one. 01:54.240 --> 02:00.570 So this light is highlighted with the blue color, and you could clearly see the reason because we are 02:00.570 --> 02:02.240 utilizing G50 night. 02:02.250 --> 02:05.280 So which is why no fly output equipment, right? 02:05.340 --> 02:10.440 And then the other thing that we have is over here, right? 02:10.620 --> 02:13.830 So this is, I guess, our next input. 02:14.070 --> 02:17.180 This data represent our output. 02:17.460 --> 02:17.760 Great. 02:19.060 --> 02:26.830 And 15 and 15 percent are in purple great, so we have the G 15. 02:28.080 --> 02:29.370 We're here, right? 02:29.790 --> 02:34.500 Then I'll put this at this position, right, and then last one is. 02:35.610 --> 02:37.440 P15, which is over here, right? 02:37.680 --> 02:42.360 So depending on the constraint that you specify, the specific location will be chosen. 02:42.400 --> 02:44.840 OK, and here we have I like. 02:44.960 --> 02:49.800 OK, so this basically represents 98 that we are employing, right? 02:50.780 --> 02:55.970 So now you understand the usage of an implementation rate, so this basically announcing this is have 02:55.970 --> 03:04.580 converted are still cool to the XP to reproduce, OK, and then when you specify construing the specific 03:04.580 --> 03:07.280 location is identified where we'll be adding. 03:07.850 --> 03:08.140 Right. 03:08.360 --> 03:14.980 So once you complete an implementation, now will go ahead and we restore Lost Bridges program and debug, 03:14.990 --> 03:15.650 OK, here. 03:15.650 --> 03:22.220 The first step is you need to upgrade to the rest of the option that you see in a synthesis and implementation 03:22.220 --> 03:24.170 will be discussing as we progress further. 03:24.950 --> 03:28.460 So if you just analyze the flow that we have in and flew, navigate it. 03:28.790 --> 03:35.780 So we completed a simulation, we completed an analysis, we completed a synthesis and now we also completed 03:35.780 --> 03:36.820 an implementation rate. 03:36.830 --> 03:40.940 And we already did this when we are working within simulation. 03:40.970 --> 03:42.830 So we'll be finding this war option. 03:42.830 --> 03:43.850 I disable there. 03:43.850 --> 03:47.790 But now we completed synthesis and an implementation rate. 03:47.810 --> 03:52.720 And due to this, you will find out that all of this for options are deliberate. 03:52.910 --> 03:59.150 And this also makes sense because we have an edge deal where we go from a behavioral verification. 03:59.150 --> 04:04.790 But when we perform a synthesis, our digital code is transformed to a primitive state, so it becomes 04:04.790 --> 04:09.020 mandatory that we verify whether our design is still working as expected. 04:09.560 --> 04:15.230 Similarly, when we consider an implementation right now, when we are having a similar design without 04:15.230 --> 04:16.610 an optimization strategy. 04:16.880 --> 04:20.900 So I think this is an implementation booth schematic that see. 04:22.020 --> 04:28.410 But in a case of a complex design where you have I an optimization strategies, you could clearly understand 04:28.410 --> 04:32.310 that there might be differences in an implementation rate. 04:32.310 --> 04:38.690 So it becomes mandatory that we also verify that it is working correctly when we implement our design. 04:39.330 --> 04:46.440 So remember, whenever you complete, the synthesis will just go ahead and again from boost synthesis 04:46.440 --> 04:47.520 function functional simulation. 04:47.530 --> 04:52.230 So this will verify whether I design the synthesis design is still working correctly. 04:52.390 --> 04:52.610 Right. 04:52.680 --> 04:54.870 So we'll go ahead and click on that option. 04:55.470 --> 04:58.110 This will again open our V for Mirror, right? 04:58.410 --> 05:03.360 And now you can see we have a possibility, OK, Libya and why? 05:03.670 --> 05:05.210 So we'll just be forcing an input. 05:05.220 --> 05:08.400 Right click Forced Log one two zero. 05:08.820 --> 05:15.840 OK, and the parade that will be choosing for any use and nine for B will again be using a political. 05:17.070 --> 05:23.970 Three hundred nine will again be evaluating all the stimulus four thousand milliseconds. 05:24.240 --> 05:27.270 So let me just verify whether our design is working. 05:27.600 --> 05:28.320 Okay, great. 05:28.710 --> 05:34.680 So when we have one one, so output should be one that is happening over here, when zero zero or two 05:34.860 --> 05:42.130 zero one zero should also give us zero, the only case that we need to verify is 018. 05:42.210 --> 05:44.150 So here we see how to this. 05:44.640 --> 05:46.080 So it is still working. 05:46.080 --> 05:46.770 Correct, right? 05:47.070 --> 05:53.130 The next step after you verify the behavior, of course, and this is functional simulation will just 05:53.130 --> 05:55.620 be going ahead and perform post implementation. 05:55.620 --> 05:56.760 Functional simulation. 05:57.790 --> 06:02.510 OK, here also will be doing the same thing for slot one two zero. 06:03.770 --> 06:04.820 Handed down the second. 06:06.090 --> 06:13.640 For me, three ending nanosecond rate and Will just getting hit on Grenfell Tower journalistic heroes. 06:13.740 --> 06:15.350 You could see the scene before, right? 06:15.360 --> 06:21.600 So our design is looking perfect in both Optus and this, as well as after implementation. 06:22.110 --> 06:24.340 Now we are ready to generate a bit. 06:24.600 --> 06:27.660 So bitstream is something that will be going on to an FPGA, right? 06:27.930 --> 06:29.330 They just hit on John Edwards. 06:29.490 --> 06:33.340 Now, since we already completed an implementation, this won't be taking much time. 06:34.920 --> 06:36.450 So our biggest deal is completed. 06:36.540 --> 06:43.110 Now it's time that you can take your heart away to your personal computer and we'll just head on open 06:43.110 --> 06:44.340 hardware management, right? 06:45.240 --> 06:50.160 So once you open and highway manager, you get an option open target, right? 06:50.160 --> 06:52.980 So you'll just be clicking on open target and an auto connect. 06:52.990 --> 06:57.960 So this will automatically identify the wall, which is connected to your PC. 06:58.650 --> 06:59.040 OK. 07:00.390 --> 07:05.700 And once your ball is identified, we will just go ahead and go grab my device, right? 07:06.150 --> 07:07.740 So you'll be fine finding we have a option. 07:07.740 --> 07:10.710 One is of extreme fighting, which is a big fight that we have. 07:10.770 --> 07:12.390 The other one is a debate. 07:12.780 --> 07:19.020 So when we add an aioli, which is an integrated logic and later use foreign hybrid debugging, there 07:19.020 --> 07:22.140 will be finding and finding analytics file inside it. 07:22.240 --> 07:24.960 Okay, since we have no formal debugging. 07:25.260 --> 07:27.690 So this is a great tool. 07:27.690 --> 07:36.230 Just click on Program FPGA and then you could also up the state on an LLC as you change the state. 07:36.440 --> 07:37.700 All right. 07:37.920 --> 07:44.010 So this completes that entire loop of an FPGA right small aggregator is very, very helpful here. 07:44.640 --> 07:49.540 So first, we have a two ways of specifying design. 07:49.770 --> 07:55.320 It may either be a text based source, or it may either be a schematic basis of state. 07:55.650 --> 08:01.380 Once you complete your source, you proceed for a functional verification by performing a behavioral 08:01.380 --> 08:02.010 simulation. 08:02.400 --> 08:06.180 Ideally, analysis gives you the first view of an ideal quote. 08:06.200 --> 08:11.580 So the typical system that you are designing, whether it is matching through the schematic that you 08:11.850 --> 08:18.170 have chosen right, then you have a synthesis or synthesis, transform your go to something that are 08:18.290 --> 08:20.820 returned the state, then you have an implementation. 08:20.820 --> 08:24.510 So before implementation, it is mandatory that you specify a constraint. 08:24.890 --> 08:25.290 Okay? 08:25.530 --> 08:31.480 And then depending on the constraint, the specific side on an FPGA will be choosing, their logic will 08:31.500 --> 08:32.100 be placed. 08:32.370 --> 08:38.520 And finally, you have a program in debug where you will be generating a bitstream, connecting FPGA 08:38.850 --> 08:42.320 and then downloading a big fight on two and FPGA. 08:43.250 --> 08:47.240 The last step will be to verify your behavior on that highway. 08:47.960 --> 08:48.170 Right?