WEBVTT 00:00.120 --> 00:05.870 We completed our simulation, the next step that we have is an ideal analysis right now here. 00:05.910 --> 00:10.440 The most important option that we frequently utilize is the schematic, right? 00:10.740 --> 00:13.890 So you'll be finding with an ideal analysis, we have a schematic. 00:14.310 --> 00:19.380 And then after we perform a synthesis, we also have a schematic and after implementation also, we 00:19.380 --> 00:20.880 have schematic rate. 00:21.070 --> 00:26.150 So two of the schematics, which are very, very useful, is the schematic that you get with an ideal 00:26.160 --> 00:29.160 analysis and the schematic that you get with the synthesis rate. 00:29.460 --> 00:33.770 So with an ideal analysis, you get the schematic that you understand, right? 00:33.810 --> 00:40.900 And when you consider the synthesis now here, your steel goal is transformed into an SPG chemical state. 00:40.920 --> 00:47.760 Finally, we have an FPGA architecture, so we need to convert a steel cooled into something that are 00:47.760 --> 00:49.020 FPGA, Mr Right. 00:49.470 --> 00:53.670 So we have a set of primitives available for each FPGA device. 00:53.970 --> 01:01.830 So synthesis transform our code into the set of primitives consisting of a sale sign in it. 01:02.190 --> 01:02.570 Okay? 01:02.670 --> 01:06.390 And that could be understood by and Fiji, right? 01:06.660 --> 01:16.210 So synthesis will represent your transformation of your input into the FPGA, these primitives. 01:16.230 --> 01:16.470 Right. 01:16.740 --> 01:24.540 Whereas schematic a represent the basic symbols that we used in a digital electronic to represent you, 01:24.900 --> 01:25.130 right? 01:25.170 --> 01:31.680 For example, here you have an simple-minded we already know the symbol for an aggregate, so this will 01:31.680 --> 01:35.090 be converting an entire system to a simple blank. 01:35.430 --> 01:40.080 So if you just go to an Italian analysis and if you analyze the schematic. 01:40.360 --> 01:45.750 So here you'll be finding the symbols that you already use in a digital electronics. 01:47.260 --> 01:53.920 OK, so here you could see this is the familiar symbol for angry, OK, and then you have this two empty 01:53.950 --> 01:56.050 and B and then we have a white right. 01:56.440 --> 02:03.070 So ideal analysis basically give you the first view of the actual court so you could just go through 02:03.070 --> 02:06.880 and analyze whether you are getting the schematic as expected. 02:07.070 --> 02:07.240 Right? 02:08.320 --> 02:10.220 The next step is the synthesis, right? 02:10.240 --> 02:15.430 No synthesis, this formula is still good to something that are journalistic. 02:15.460 --> 02:15.690 Right. 02:15.700 --> 02:21.450 So we just need to perform a synthesis and we'll be using the default option or we're here, right? 02:22.950 --> 02:29.490 Sonar synthesis is completed, right, so will just be opening up synthesise design, so you have an 02:29.490 --> 02:34.840 option to open the synthesized design from here, or we could just go ahead and click on this open to 02:34.920 --> 02:41.190 this is to say this will automatically open synthesis design right now. 02:41.190 --> 02:45.910 Here you could see the default view that we get is the package, right? 02:45.930 --> 02:49.580 So there's all reprising the pen that you have, right? 02:49.770 --> 02:55.710 So we would just work on any wall of things and then you could say no, that there's been no eat well 02:55.950 --> 03:00.930 and side, and it also specify the bank well, we do not worry much about this. 03:01.290 --> 03:03.830 The second view that you get is the device rate. 03:03.840 --> 03:06.120 So here you can see AI logic. 03:07.700 --> 03:13.460 So this is an FPGA time that we have, right, so we haven't yet specified the constraint. 03:13.520 --> 03:21.070 OK, and then after that, clearly we believe we do see that logic has been added into an entirely computer. 03:21.330 --> 03:21.450 Right. 03:21.710 --> 03:25.530 So these are the two default something which is very important in this, right? 03:25.550 --> 03:30.440 So you, by default, get an iReport view where you go to a skill level. 03:30.470 --> 03:35.630 You could clearly see all the food that you have in your design to really represent an input. 03:35.630 --> 03:36.680 And why represented that? 03:36.680 --> 03:37.370 All right? 03:37.940 --> 03:43.060 If you do not able to find this view, you could just go to a layout and select a nice blend, right? 03:43.070 --> 03:45.680 So this will automatically bring a package device. 03:46.700 --> 03:46.970 Right? 03:47.390 --> 03:54.620 Now here you have a package to package been replacing the three footer bin that you have one in a 3G 03:54.830 --> 03:56.600 where you want to connect this input. 03:56.670 --> 03:56.850 Right. 03:56.870 --> 04:03.890 So since this tool represents an input, will be connecting this to a switch and to the elite, right? 04:04.190 --> 04:06.140 So you could just go ahead. 04:07.130 --> 04:11.500 And look for the specific master, it's justified. 04:11.730 --> 04:16.980 So here I am utilizing disabled six seven one zero, so I just search for a monster. 04:16.980 --> 04:17.780 It's justified. 04:18.060 --> 04:18.380 OK? 04:18.560 --> 04:23.870 And most probably will be finding next to see file is available on data, right? 04:24.140 --> 04:27.740 You can just go in and then you have a search. 04:27.740 --> 04:31.310 As far as searches, you have this unique number, right? 04:31.310 --> 04:38.330 So for Switch zero, you have 50 and be 50 to this present in the package. 04:38.570 --> 04:40.070 So we'll just go ahead. 04:40.640 --> 04:45.020 And here we will specify 50 and 50. 04:46.360 --> 04:52.060 So some of the peripheral names are also mentioned on, so this is the development that you are utilizing. 04:52.390 --> 04:57.160 OK, so here you could see we have our full switches, right and the few ladies over here. 04:57.160 --> 05:03.670 So just below the switch, OK, you could find out that this is a switch number three and the unique 05:03.670 --> 05:05.940 package bin to which it is connectivity. 05:05.990 --> 05:09.850 So 16, the blue 13, 15 and 50, right? 05:09.860 --> 05:13.400 So this represent the S.V. of finding the pin number right. 05:13.400 --> 05:18.640 So not although they will have this VIN number been mentioned, but variable they have mentioned. 05:18.640 --> 05:21.310 You could always utilize the gourmets. 05:21.310 --> 05:23.970 You go ahead and look for a master file. 05:24.010 --> 05:30.970 They will be finding all the peripheral information, but for a simple Typekit like switch leads the 05:30.970 --> 05:35.980 push button so you could always look for the unique number, right? 05:36.020 --> 05:41.110 And just next to the Pettiford in the back to here, you would see we have an Elite Three, which is 05:41.110 --> 05:42.460 connected to the right. 05:42.460 --> 05:44.560 So this elite is connected to pin number. 05:45.130 --> 05:53.140 So that is what we will be specifying over here and see that the default level which is chosen for a 05:53.140 --> 05:55.000 new standard, you just change it, right? 05:55.420 --> 06:00.540 So I'll be changing it to the max intensity that is and we see most territory. 06:00.550 --> 06:05.220 So this basically represents that we are considering applying three point table. 06:05.350 --> 06:05.650 Right? 06:06.130 --> 06:07.100 So this completes. 06:08.650 --> 06:10.360 Process of adding a continuing rate. 06:10.630 --> 06:16.540 So in our absolute school, we have Eby I like and we are able to connect it to the FPGA instead is 06:16.540 --> 06:17.710 chief of 2015. 06:17.710 --> 06:21.370 And so this is what is mean by a constrained flight. 06:21.370 --> 06:22.500 So to create a constraint. 06:22.990 --> 06:29.050 After you specify design and scalable, you just need to see your less control less and. 06:30.070 --> 06:32.880 Given into a fight, so we'll just be naming this has stop. 06:33.220 --> 06:34.930 We'll get now if you go to a small step. 06:35.230 --> 06:37.080 So with a scene? 06:37.210 --> 06:37.990 OK, hold it. 06:38.410 --> 06:41.410 Now you have a talk to do so if you just open. 06:41.710 --> 06:43.200 You could say no, that are. 06:43.220 --> 06:49.440 All the codes are connected to the respective rates of this complete AH, synthesis. 06:49.450 --> 06:56.740 OK, so synthesis basically transform your article code to the FPGA to make it data that could be understood 06:56.740 --> 06:58.510 from an necklace also. 06:58.590 --> 06:58.820 Right. 06:58.840 --> 07:03.520 So you have a series of nets and then you have a sense, right? 07:03.530 --> 07:10.000 So selling through the Input-Output buffer and the anchor trade, so which is implemented with the help 07:10.000 --> 07:10.960 of it and you? 07:11.350 --> 07:11.590 Right? 07:12.400 --> 07:15.010 So it is basically as an internal substrate. 07:15.400 --> 07:18.130 The next important thing to realize is the schematic. 07:18.160 --> 07:21.220 So let me just go ahead and try to find out the schematic. 07:22.710 --> 07:28.260 So now if you analyze this schematic, which is available in a synthesis, you could clearly see this 07:28.260 --> 07:31.110 is different than what we've seen in our analysis, right? 07:31.800 --> 07:36.670 So this is how your school will be transformed into something that you are if you are listening right 07:36.670 --> 07:43.740 to L.A., I don't know mental block that you have in Fiji and which I utilize implement a logical extraction, 07:43.740 --> 07:44.010 right? 07:44.010 --> 07:45.670 And then you have a series of buffer. 07:45.780 --> 07:46.020 Right. 07:46.320 --> 07:49.530 So this complete the synthesis, the process of synthesis. 07:49.530 --> 07:54.990 And now remember, before performing and implementation, we must specify the constraint side so that 07:55.290 --> 08:00.160 they are required to choose the specific side on Fiji. 08:00.180 --> 08:01.700 They are logic will be placed.