WEBVTT 00:00.180 --> 00:05.630 I assume that you probably have at least used one of the microprocessor or a microcontroller. 00:06.270 --> 00:12.230 OK, so let us see what is the procedure to change the clock speed? 00:12.460 --> 00:19.110 OK, in an MSP before 30, which is also a very popular microcontroller, I guess we in general have 00:19.110 --> 00:23.940 a DCO, OK, or Liscio basically mean our digital controller oscillators. 00:23.950 --> 00:29.370 You get the flexibility of controlling the clock speed by changing the register. 00:29.760 --> 00:31.200 So if you just go. 00:33.360 --> 00:40.410 What we are doing is we are setting certain bits of our digital control oscillator so we have control 00:40.410 --> 00:47.520 registries where we are setting up the clock speed that we are in general. 00:47.520 --> 00:53.490 If we considered to change the clock frequency, we should have a good idea about the registers which 00:53.490 --> 01:01.140 are present in this specific microcontroller architecture and then how you calculate the values of the 01:01.140 --> 01:07.140 bet that should be updated in the register to have a dedicated clock rate and which is not that much 01:07.140 --> 01:10.890 easy, but with a good experience, you can do it very easily. 01:10.890 --> 01:11.130 Right. 01:11.580 --> 01:16.640 So this is how in general we change the clock speed when we work with microcontrollers. 01:16.970 --> 01:21.450 So we have a dedicated controller registers depending on the requirement. 01:21.450 --> 01:25.380 We set the parameters and then finally we get an output. 01:25.380 --> 01:30.390 Croxford Right now, if we want to analyze a seam situation in an FPGA. 01:30.620 --> 01:36.010 OK, so let's assume that we have clock of on board, clock of hundred megahertz. 01:36.010 --> 01:41.840 So this Alred megahertz basically mean the clock period is a ten nanosecond rate. 01:41.850 --> 01:44.670 So this is the clock that we have now. 01:44.670 --> 01:49.560 Let's assume that we want to have a frequency of twenty five megahertz. 01:49.740 --> 01:50.190 Right. 01:50.970 --> 01:53.930 So we want to have a period of 40 nanoseconds. 01:54.270 --> 01:55.290 So if we just go ahead. 01:55.530 --> 02:00.590 So if you divide and hundred megahertz by twenty five megahertz, we get the value of four. 02:00.600 --> 02:03.180 So for basically mean the half value is two. 02:03.540 --> 02:09.780 So here if I just replace this four with one, so why we have replaced it this with one, because we 02:09.780 --> 02:12.930 want to have account value of this account value. 02:12.930 --> 02:20.070 How we are computing account value is it is basically the ratio of the clock frequency that we have 02:20.070 --> 02:22.530 on an FPGA to a desired frequency. 02:22.560 --> 02:24.790 OK, that is a hundred divided by twenty five. 02:25.260 --> 02:26.880 Give us four. 02:27.030 --> 02:33.690 So here cound basically represent the half value that you get when you divide the frequency that you 02:33.690 --> 02:36.730 have on an object to the desired clock frequency. 02:36.750 --> 02:43.680 So for example, in our case we have an on bearclaw frequency of hundred pingers and the desired frequency 02:43.680 --> 02:44.630 is twenty five megahertz. 02:44.630 --> 02:48.690 So if you just take a ratio of this two, it will be getting a factor of four. 02:48.870 --> 02:51.300 So half of it is OK. 02:51.540 --> 02:56.260 So when we say count is less than one, so we are getting to value that is zero nine one. 02:56.370 --> 03:00.390 So that is how we represent the account value inside the second variable. 03:00.820 --> 03:05.160 Now let me just try to perform a simulation and see what happens. 03:05.400 --> 03:05.770 OK. 03:05.790 --> 03:11.140 So here now what I do is first I'll meet you then in frequency. 03:11.160 --> 03:14.970 So this is an input clock and then we have this as an output clock. 03:15.180 --> 03:18.660 So if you measure the period of an input clock. 03:18.660 --> 03:19.050 Right. 03:19.350 --> 03:24.120 Which is very, very simple to do, what we will do is will just measure the rate. 03:24.340 --> 03:29.160 So it is ten nanoseconds or ten nanoseconds basically corresponds to an hundred. 03:29.560 --> 03:30.090 Say this. 03:30.090 --> 03:34.500 We previously discussed ten nanoseconds, hundred megahertz. 03:34.650 --> 03:42.660 OK, and now we have designed a very local to achieve an output frequency of twenty five megahertz. 03:42.660 --> 03:48.510 So it should have a period of 40 nanoseconds just trying to measure the clock output. 03:48.680 --> 03:52.970 OK, so if you just try to measure he'll be noticing it is 14 and a second rate. 03:53.130 --> 03:58.920 So just adding a different count while you can get the output clock frequency. 03:59.070 --> 04:08.220 If the ratio of the clock frequency that you have on an FPGA to the desired clock frequency, give out 04:08.220 --> 04:08.760 an integer. 04:09.060 --> 04:16.230 So, for example, let us assume that, you know, you want to have and desire frequency of ten megahertz. 04:16.260 --> 04:22.380 So in this case, if you divide hundred, we go to ten mega to get the factor of 10 and the half of 04:22.380 --> 04:23.520 Dennis vibrate. 04:23.550 --> 04:30.060 So here, if we just replace one with four and if you just try to again, relaunch a simulation and 04:30.060 --> 04:31.700 now if I just try to measure. 04:31.710 --> 04:35.350 So let me just try to measure the clock period. 04:35.370 --> 04:35.970 So here. 04:38.280 --> 04:47.400 If I just try to measure the clock period, so it is around 100 nanoseconds, so if you and put out 04:47.400 --> 04:52.850 and make out, so here you'll be noticing that we get ten hundred nanoseconds. 04:53.100 --> 04:59.460 So this is how it becomes very easy to get an output desired output frequency. 04:59.460 --> 05:05.790 If the fact that we get when we take the issue of the FPGA clock frequency to the desired clock frequency 05:05.790 --> 05:08.010 as an integer value if we get a fraction. 05:08.070 --> 05:14.850 But let us assume that we want an output frequency of thirty three megahertz right now will be finding 05:14.850 --> 05:15.690 in this situation. 05:15.690 --> 05:17.570 We do not get an integer value. 05:17.580 --> 05:19.050 Instead we get a fractional value. 05:19.080 --> 05:20.870 So in that is what you do, right. 05:21.090 --> 05:29.850 So you can just go to an IP catalogue and then there if you just search for a clocking result. 05:31.130 --> 05:31.610 OK. 05:33.650 --> 05:43.930 And there if you just go to the output clock, so here we can actually specify, let us assume thirty 05:43.940 --> 05:50.150 three megahertz, OK, we just need to go ahead and generate an IP. 05:50.150 --> 05:52.610 So will be finding that now. 05:53.610 --> 06:01.500 With adding an IP, we can also read the clock frequency where the issue is a fraction, right? 06:01.740 --> 06:08.890 So this is how it becomes very easy to generate a desired clock out of an FPGA and then microcontroller. 06:08.910 --> 06:14.040 We generally need to have a good understanding of an architecture and how you configure the registry 06:14.040 --> 06:14.500 as well. 06:14.730 --> 06:18.090 But here we will be finding we just need to work on pure mathematics. 06:18.090 --> 06:24.540 So if we get an integer when we divide our FPGA clock frequency to their desired frequency, then we 06:24.540 --> 06:27.210 can simply replace discount value. 06:27.390 --> 06:31.820 OK, over here, as you change the number, you will be getting a very low frequency. 06:32.220 --> 06:38.940 And whenever you get a fractional part, just go ahead with the locking, with our IP and you will get 06:38.940 --> 06:40.860 the desired frequency out of an.