WEBVTT 00:00.170 --> 00:05.580 Let us try to understand some of the fundamental differences that we get between an architecture of 00:05.580 --> 00:08.850 a microcontroller and an architecture of an FPGA. 00:09.000 --> 00:15.570 OK, so we'll consider it a very fundamental microcontroller, OK, which is an art, a no no. 00:15.600 --> 00:21.480 And here what I did is I've written one code just to trigger analogies which have been connected all 00:21.480 --> 00:22.830 and different digital open. 00:22.840 --> 00:29.820 So if you just go through the circuit diagram, you'll be finding that we have an already a. been connected 00:29.820 --> 00:31.800 at been number 13 to 11 11. 00:32.050 --> 00:32.190 Okay. 00:32.310 --> 00:37.300 So our agenda is basically to generate a square waveform on this three digital open. 00:37.440 --> 00:43.170 So here we have set up the pin mode as an output since we want to send the signals to analogy. 00:43.440 --> 00:50.280 And then what we are doing is we are writing a digital high on number 13, then we are waiting for one 00:50.280 --> 00:51.020 second delay. 00:51.240 --> 00:53.880 OK, and then again, we are turning it off. 00:53.910 --> 00:59.040 So this basically give us a blinking effect on an already at an interval of one second. 00:59.050 --> 00:59.330 Right. 00:59.910 --> 01:06.630 And similarly, the same logic we have utilized for writing a values to the ladies, which have been 01:06.630 --> 01:08.830 connected on PIN number two as well as 11. 01:08.850 --> 01:17.120 So if they just try to execute a call, OK, and observe the circuit, you'll be noticing that for stability, 01:17.520 --> 01:21.870 the real return on, then you have green vittone on and off. 01:22.050 --> 01:25.160 And then finally you have a plurality which beento. 01:25.160 --> 01:25.500 No, no. 01:25.630 --> 01:32.910 OK, so we have written some lines of code and from the behavior that we are getting on any leads, 01:32.970 --> 01:36.750 you can easily guess that the code is executing in a sequential manner. 01:36.760 --> 01:37.030 Right. 01:37.050 --> 01:43.260 So the Stutman, which are written first, will be executed and then we have other Stutman being executed. 01:43.260 --> 01:43.610 Right. 01:44.100 --> 01:48.570 So this is what we refer to as a sequential architecture of a microcontroller. 01:48.600 --> 01:55.050 Right now, what we'll do is we'll write some very low code and see how FGB is right. 01:55.080 --> 01:57.130 So here we are inside and we will do it. 01:57.300 --> 01:59.260 That will be using throughout the course. 01:59.260 --> 02:01.350 So here I have written to code. 02:01.380 --> 02:07.890 OK, so one of the code will just try to execute without worrying much about the code right now, since 02:07.890 --> 02:14.100 as you progress in, of course you'll be getting an fundamental understanding of whatever we have written 02:14.100 --> 02:14.330 here. 02:14.340 --> 02:14.640 Right. 02:15.060 --> 02:16.880 So do not worry much about the code. 02:16.920 --> 02:20.610 What will be doing is first we try to execute this. 02:20.910 --> 02:27.600 OK, so here we have certain set of statements that we have written and our agenda is just to see the 02:27.600 --> 02:30.010 code and perform our simulation. 02:30.060 --> 02:35.670 So if you observe and we form that we are getting with the code that we have written, you will be finding 02:35.670 --> 02:41.610 that all the free signals we are getting on an output would execute in parallel. 02:41.940 --> 02:49.710 OK, so at the same instance she will be considered similarly at same instance we get our G and Y being 02:49.710 --> 02:50.190 turned on. 02:50.220 --> 02:55.320 So if we compare this with the sequential architecture that we discussed previously, it will be finding 02:55.320 --> 03:02.670 there is no way to get a parallel architecture or the multiple segments running at a parallel when we 03:02.670 --> 03:04.140 consider the microcontroller. 03:04.140 --> 03:09.720 But with an SPG and a very low, we can write a code which can execute in a battle. 03:09.750 --> 03:19.860 OK, so this is why often we refer to an FPGA as having a parallel architecture, because even though 03:19.860 --> 03:28.680 you have written the code with a series of Stutman, but the architecture of an FPGA works in such a 03:28.680 --> 03:30.090 way that you'll be finding. 03:31.640 --> 03:37.710 All the signals are being generated in a parallel or on the different outputs. 03:37.790 --> 03:43.520 OK, but let us assume that you have a situation where you want to have behavior. 03:44.450 --> 03:46.850 Of a system working in a sequential manner. 03:46.880 --> 03:49.490 OK, so if I just commend the school out. 03:51.040 --> 03:57.510 OK, and if I just uncommented the other quote that we have written will be finding something interesting, 03:57.790 --> 04:03.980 I guess we'll just uncommented this and will again perform a simulation. 04:04.150 --> 04:08.860 And now if you observe a waveform, you'll be noticing that. 04:10.250 --> 04:17.480 If I just try to zoom in a bit, OK, you'll be finding that we have modified our goal and we able to 04:17.480 --> 04:19.130 get the sequential nature. 04:19.200 --> 04:24.860 OK, so the very log and FPGA architecture are so much flexible that depending on the requirements, 04:24.860 --> 04:28.180 they can behave as in parallel architecture. 04:28.190 --> 04:32.840 But all the signals will be simultaneously generating a signal, if you want. 04:33.110 --> 04:38.380 Or you can write a code such that it starts to behave as a sequential manner. 04:38.390 --> 04:45.410 And that is the flexibility that we get with an FPGA that it can show the nature similar to a microcontroller 04:45.590 --> 04:53.510 or it can show a nature exactly opposite to your microcontroller that is behaving in a parallel manner.