WEBVTT 00:00.180 --> 00:06.600 So let us try to summarize an FPGA architecture so that you have an AI which controls the functionality 00:06.600 --> 00:11.640 of an AI visibility, mapping the specific needs of an eye opener. 00:11.990 --> 00:13.960 So that will be connected to an object. 00:14.370 --> 00:19.740 Then we have a SILVIS, which are the centralized resources for implementing a logic function, and 00:19.740 --> 00:21.150 then we have a switching matrix. 00:21.690 --> 00:28.380 So they are used to communicate the data between CLB and to implement a complex functionality inside 00:28.380 --> 00:28.930 a CLB. 00:29.580 --> 00:36.920 We have a few slices and then each slice can have a multiple and so forth. 00:37.110 --> 00:39.050 Each slice consists of utilities. 00:39.360 --> 00:45.360 Now there are different kind of slices, so 50 percent of the slices are six, whereas twenty five percent 00:45.690 --> 00:46.950 are slice. 00:48.300 --> 00:56.760 So slices are capable of implementing logic function as well as they also have a full flow for a slice. 00:56.760 --> 01:02.070 And other, on the other hand, have a white multiplexed which can be used to extend the capabilities 01:02.070 --> 01:08.270 of the input as well as you also have a carriage in logic that can be used to speed up an automatic 01:08.310 --> 01:14.430 operation, slice him on the other hand, along with the capabilities that slice and how they have a 01:14.430 --> 01:19.860 specialized luti which can be which can be configured to work as a distributor. 01:20.430 --> 01:22.220 So this is the type of slices. 01:22.230 --> 01:28.440 So 50 percent of the slices of slice X, whereas twenty five percent of slices slice it and then slice 01:28.440 --> 01:28.590 it. 01:28.620 --> 01:35.430 So this also suggests that there is a limitation on the maximum memory that you can generate out of 01:35.890 --> 01:36.120 this. 01:36.180 --> 01:36.320 Right. 01:36.930 --> 01:42.660 So to summarise, this is how a typical architecture looks so green color basically. 01:42.660 --> 01:54.480 And then blue color is an kelby's that we also have a memory controller that are used to control an 01:54.480 --> 01:55.500 external membrane. 01:55.510 --> 01:58.130 Sources other than that, the red color. 01:58.140 --> 02:01.240 We have a dedicated memory which doesn't block Ramogi. 02:01.250 --> 02:07.530 So this is not been implemented from the CLB, but a dedicated memory resources that is available on 02:07.530 --> 02:08.160 an FPGA. 02:08.280 --> 02:15.390 OK, we also have DSP slices to speed up a signal processing application and at the center we have a 02:15.390 --> 02:23.400 clock management system which handle all the clock related operations such as synthesis, generation 02:23.400 --> 02:26.470 of a clock and then changing office and so on and so forth. 02:26.490 --> 02:35.510 We also have breaking point to speed up our PCI to handle PCI operations with the gigabit transfer rate. 02:35.910 --> 02:43.720 So this is how a typical budget look, or if you look at this, all of the resources that are on our 02:43.730 --> 02:44.810 on and FPGA to. 02:49.600 --> 02:57.960 OK, so just to summarize, on the on the periphery, we have an aisle blocks then that is at the center 02:57.970 --> 03:04.090 we have a clock management, which basically this group of clock to all the resources of an FPGA. 03:04.420 --> 03:12.760 We also have a -- point to handle transactions, memory dedicated memory controller, two to communicate 03:12.760 --> 03:13.150 with then. 03:14.640 --> 03:16.200 Memory devices such as. 03:17.190 --> 03:25.640 Then we also have a CLB Sushmita with the then we have a Sylves which are shown within a blue color 03:25.650 --> 03:33.070 over here, small rectangular boxes, the dedicated memory available on an FPGA we just have. 03:33.240 --> 03:39.000 So this memory is not being implemented from the slices, but a dedicated memory resources which even 03:39.000 --> 03:41.860 though are limited but still can be utilized independently. 03:41.880 --> 03:48.840 OK, the saffron color either slices which are used to boost up the signal processing application and 03:48.840 --> 03:50.460 then we have an buffer's. 03:50.910 --> 03:54.060 OK, so this is how a typical FPGA di look. 03:54.930 --> 04:01.200 And then you already have no idea about what is inside and every company right now, we are ready to 04:01.200 --> 04:02.610 proceed with understanding and.