WEBVTT 00:00.060 --> 00:05.680 So the good thing about the multiplexed is so the along with the retail sector can be helped to implement 00:05.680 --> 00:10.510 the logic function so we can use them to implement conventional logic function. 00:11.070 --> 00:15.930 So let us try to understand some of the fundamentals so that we can proceed to an actual leadership, 00:16.320 --> 00:23.160 because in an FPGA we have different type of multiplexed and that can be used to implement different 00:23.850 --> 00:30.090 combinations of logic and that we have a restriction on the number of input that we can actually feed 00:30.090 --> 00:30.710 to an entity. 00:30.750 --> 00:33.300 So to understand that, we consider a very simple example. 00:33.840 --> 00:37.300 So, for example, let's assume you have this mix, right? 00:37.320 --> 00:41.120 So you have two is two one mux. 00:41.490 --> 00:48.660 OK, now, since we have two inputs, OK, so we have a select single select line which is having a 00:48.660 --> 00:52.720 size of a single bit, and then we have this output line. 00:52.980 --> 01:01.230 Right now, if you consider that this is you, we can take the issue here, which is one of the variable 01:01.740 --> 01:04.730 inside of a function and be here. 01:04.920 --> 01:05.220 Right. 01:05.240 --> 01:12.510 So if we have this kind of configuration, so here y will be equal to Y will be equal to if you know, 01:12.510 --> 01:14.850 since this is and this is connected to a zero. 01:15.030 --> 01:20.400 So Y will be close to it, but right to when we will be having values in zero. 01:20.670 --> 01:21.510 So ever. 01:21.510 --> 01:28.280 And that is multiplied with the V and for the next case it will be to be right now we already know that 01:28.290 --> 01:33.180 as an input, so we cannot connect any variable because we have an altitude here. 01:33.210 --> 01:41.130 So if you remember the structure, we have an L.A. where we'll be studying a single bit and then we 01:41.130 --> 01:42.340 have a mux. 01:42.360 --> 01:42.580 Right. 01:42.600 --> 01:48.140 So this is a typical structure, often slice inciting a feature. 01:48.810 --> 01:52.110 So we cannot we cannot connect a variable here. 01:52.140 --> 01:55.650 So in that case, there is a room that this can only take a value of. 01:55.650 --> 01:56.260 One, two. 01:56.490 --> 02:00.470 OK, so we can have any one or two value here. 02:00.480 --> 02:08.220 So the number of input that we can connect actually with an entity and the structure that we have inside 02:08.220 --> 02:10.430 a slice of an FPGA is only one. 02:10.440 --> 02:10.700 Right? 02:11.430 --> 02:16.650 If we consider the normal logic family or a normal digital circuits, we can actually going to agree 02:16.650 --> 02:19.860 with one of the variable over here available here. 02:19.860 --> 02:27.690 But with the architecture that we have fought in FPGA since we already have any luteal here, we. 02:28.910 --> 02:33.180 Do not have any other choice to connect only a single variable. 02:33.210 --> 02:41.720 All right, so the number of select line they're operating on, the mux decide how many inputs you can 02:41.720 --> 02:43.580 feed to a specific. 02:43.630 --> 02:49.070 And right now we can go to shoot and understand more on this. 02:49.070 --> 02:49.360 Right. 02:50.570 --> 02:53.300 So here we are inside a Spartan 60. 02:53.800 --> 02:58.340 OK, so this is one of the structure of a slate, so you can notice we have a slice. 02:59.360 --> 03:05.200 And then here I'll be noticing that we have a bus which is having the size of six bitrate. 03:05.210 --> 03:10.350 So these are basically the select line that are present on the mux, which is present afternoon. 03:11.120 --> 03:15.230 So we can connect six in pulldown here then. 03:16.280 --> 03:22.620 We have one more, Élodie, which again consists of a six inputs so we can actually succeed here. 03:22.870 --> 03:27.530 OK, and then finally to select this, we have an F seven B Muxtape. 03:27.950 --> 03:34.700 So inside a single space utilizing two Elwood's, we can actually fit 12 inputs and considering one 03:34.700 --> 03:42.320 more select line that we get out of seven B mux, we have in total 13 inputs that can be connected to 03:43.460 --> 03:48.590 that can actually be connected over here or it can actually be used eight to one. 03:48.770 --> 03:53.520 So these are two possibilities are that either you can feed a 13. 03:53.540 --> 04:02.000 So if you utilize this F seven, B, instead of having the six input logic function, you can actually 04:02.000 --> 04:04.970 extend it to 13 the logic function. 04:05.000 --> 04:07.730 OK, so this is how you extend your capabilities. 04:08.120 --> 04:11.840 And then again, you have the capability to actually distribute output. 04:12.380 --> 04:13.820 So that is also possible. 04:14.040 --> 04:24.260 OK, so each slice it slice actually consists of four legs, OK, and each is capable of handling six 04:24.260 --> 04:24.710 inputs. 04:24.740 --> 04:28.190 OK, so you'll be noticing you can have two independently. 04:28.190 --> 04:38.840 This one looks out of a slice or you can actually have a 13 to 13 with input functions that can be actually 04:38.840 --> 04:40.400 implemented out of this slice. 04:40.640 --> 04:43.800 Or if you do consist of other books such as Effect. 04:44.270 --> 04:52.730 OK, so if we utilize effort capability, you'll be noticing that here we also have an effect Maxo here. 04:53.040 --> 04:59.120 OK, so if you don't to the first case when we want to implement the mux out of this slice so we can 04:59.120 --> 05:00.350 actually combine this for. 05:01.010 --> 05:06.950 OK, and considering this three maxus which are being utilized, we actually get six to one. 05:07.390 --> 05:08.900 So that is one of the possibilities. 05:09.200 --> 05:11.800 In a previous case, if utilised, learn. 05:12.170 --> 05:19.160 OK, and then single F seven months you have it two one eight to one mux configuration. 05:19.400 --> 05:25.850 But if you combine all the foodless inside a single slice, you can either have a 16 to one box, which 05:25.850 --> 05:31.060 is a one off the B of implementing a maximum FPGA. 05:31.400 --> 05:36.460 Or the other thing that you can actually implement is the multi input logic equation. 05:36.680 --> 05:40.790 So we need to just find out what how many inputs that we can actually feed. 05:40.880 --> 05:48.110 OK, so here 16 Frankenfood here also we can feed six year olds, we can feed six input here also we 05:48.110 --> 05:49.060 can feed six input. 05:49.370 --> 05:54.740 So in all here we have a twenty four inputs and then we also have a three select total. 05:54.980 --> 05:57.380 We can feed twenty six input logic equation. 05:57.470 --> 05:58.450 OK, so slice. 05:58.790 --> 06:09.110 So if you summarise for a Spartan's six family slice, ok, slice can actually be utilized in the food. 06:09.560 --> 06:13.190 OK, so there are four simple implementation which are possible. 06:13.190 --> 06:14.540 Either you can have two. 06:16.450 --> 06:18.820 In input, logic, accretion. 06:20.490 --> 06:23.530 Logic equation, which can be implemented out of it. 06:23.820 --> 06:26.380 In fact, we can have 16 to one Max. 06:26.400 --> 06:33.440 OK, that is one of the possibility signals as to and that is the third possibility single do this, 06:33.450 --> 06:33.630 too. 06:33.630 --> 06:39.810 And that is the third possibility we have and find a possibility that we have is an implementing 17 06:39.810 --> 06:40.250 and both. 06:41.690 --> 06:44.180 Combination of equation or the logic equation?