So we'll start with an or so on the edge.
So on the edge, we have an eye socket.
So we have an ICU.
Locks which are present.
OK, on all the edges, they may be present depending on the chip package that you are utilizing.
OK, so we have an array of blocks that are present on an edge.
OK, and then we have and logic blocks which are used to implement the logic functionality.
And for Xilinx FPGA, the art of design configurable, what you learned assume that there are four configurable
logic blocks that we are designing.
Right.
So that we do that we are discussing consist of a food logic block.
OK, and then finally, to implement complex equations or complex functionality, we would really be
having an interconnection between this specific CLB.
So that is handled entirely by an switching matrix or any interconnection.
So this are the interconnection metric which handed the connection between this to Silvis, this to
have a complex functionality.
Right.
Now let's understand what is inside a CLB So inside a CLB, we have multiple slices.
OK, so we have multiple slices, but they are also not a fundamental component which are used to use
to develop a logic inside an FPGA.
So each slice can have multiple.
And so finally, Angellotti is something which is a fundamental block behind designing and developing,
and zaitchik functions on a future.
So we haven't let us assume that we have to input Lutece to input Lutece.
So these are some simple single Strand says, OK, so to input basically if you consider two input.
So we have four unique values.
OK, so that will be four memory location that will be present inside.
And they do this right.
So.
Let us assume that we have an alibi, which consists of a four location.
So then we have a few that are coming out of this.
So these are the symbolism where we can either save one order so we can store one or two inside the
system and then let us assume that we have connected and mux over here.
So it is basically fortressed when monks OK, and then we can decide whether to have a combination of
circuit or to implement the sequences.
So in that case, we're required to have flipflopped.
So we also have flip flop so you can decide which path to follow.
So you again can add one looks and then you can either take this combination output and then you can
also have a provision prior to sequential output.
And finally, you feed this to and I block it.
So this is what a simple destructiveness.
OK, so now slices the slices can have multiple Allardice.
Now these can have different capabilities.
So for example, for an effigy which are belonging to a version less than seven series, they all have
a food input.
It looks OK.
So when you see food input, so basically you have 16 memory location where you can store a single big
one or zero and then you have full control pins.
So here since we have four.
Connection or food inputs for a mux, we can have a selection of, say, stupid right now to implement
a logic functionality is is pretty interesting.
So, for example, let's assume that we wish to implement this function y equals to EB if we just or
if I just go to the next step to discuss more on this.
OK, so let's assume that we are implementing a combination of toked.
OK, and we have an equation like this, Y equals two.
So here now if I just make a table out of this equation, so it becomes very simple.
So we have a B and then we have Y so big and powerful combination, one zero and one.
So we know that when one spell the end, we are one.
We should send Y to the rest of the cases we have C..
So if you considered OK, so if it consists of doing utility, ok, do it consists of brutality.
We have a food location which are further connected to mux.
Right.
And then the select line basically feeding to an input rate.
And then since this is a combination of circuit two will follow, we, we can exert influence over the
rest of the thing.
And then this is going to block an output by where we have assumed that we have connected.
And so now we know that we will be connected and be here.
So once and we both one.
So we'll be selecting this location.
Right.
And in that case, we wondered why should be close.
And so for that reason, if we just feed one or two here and if we program the rest of the bits for
the cell to be zero, we knew that then one two four zero zero here.
So this the content that we have with this cell will be selected.
We'll be getting close to zero if we apply 012 here.
So this content will be given out on an YPO.
Still will be getting through.
If you apply one zero, we will still be getting zero.
But once we apply one one, this self-contained will be sent to invite and we'll be getting one.
So this is how simple logic operates in the next question comes is how you.
So this is what is happening when we are performing or when we are programming.
So when you are programming or doing your configuration of an object.
So one of the things that happens is all the stem cells, depending on the logic that are implemented,
are being initialized to the required logic.
So if I assume that you are implementing this function on an FPGA to one of the elements which will
be selected out of the slices, the number of slices present on that FPGA, depending on Diable that
you have specified in the industry, and then this contained will be written in a configuration Stipek.
So when we run our application, we'll be having this content will always be a fix and we'll just be
changing A and B this.
And according to that, you'll be getting a value.
OK.
So now you understand one of the processes that happened during the configuration of programming will
often produce the same basis which are used to implement and are being updated with the value depending
on the logic function that you are implementing.
Other key points that you can notice.
The fundamental blocks that are used to implement a logic function inside an FPGA is and, you know,
there may be multiple ill-suited inside a slice and then we have a seal.
So there may be multiple slices that are present inside seal.
So if you just go to an architecture so we have a CLB, which is a block that is used to implement the
logic functionality on.
And if you do so, CLV consists of multiple slices.