library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

entity top is
    Port ( clk : in STD_LOGIC;
    sclk : out std_logic;
    mosi,cs : out std_logic;
    start : in std_logic
    );
end top;

architecture Behavioral of top is
signal setup_data : std_logic_vector(31 downto 0) := X"8000_0001";
signal data : std_logic_vector(31 downto 0) := X"030F_FF00";
-------------Clocking Process --------------
signal countclk : integer range 0 to 51 := 0;
signal tsclk : std_logic := '0';
--------------------------------------------
-----------Data generation -----------
type state_type is (idle,setup,collect,trans,check);
signal state : state_type := idle;
signal tcs, tmosi : std_logic := '0';
signal count : integer range 0 to 33 := 0;
-------------------------------------
begin

slower_clk_gen: procesS(clk)
begin
if(rising_edge(clk)) then
if(countclk < 50) then
  countclk <= countclk + 1;
else
  countclk <= 0;
  tsclk <= not tsclk;
end if;
end if;
end process;


data_gen:process(tsclk)
begin
if(start = '0') then
tcs <= '1';
tmosi <= '0';
elsif(rising_edge(tsclk)) then
case(state) is

when idle =>
tcs <= '0';
tmosi <= '0';
state <= setup;

when setup =>
  if(count < 32) then
    tmosi <= setup_data(31 - count);
    count <= count + 1;
  else
     tcs <= '1';
     state <= collect;
     count <= 0;
 end if;
 
 when collect =>
    tcs <= '0';
    data <= data;
    state <= trans;
    
  when trans =>
   if(count < 32) then
     tmosi <= data(31 - count);
     count <= count + 1;
   else  
      count <= 0;
      tcs <= '1';
      state <= check;
   end if;
  when check =>
     if(start = '1') then
       state <= collect;
      else
        state <= idle;
      end if;
 when others =>
   state <= idle;  
end case;
end if;
end process;

sclk <= tsclk;
cs <= tcs;
mosi <= tmosi;

end Behavioral;