library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;


entity memory_tut is
Port (
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
we,oe : in std_logic
 );
end memory_tut;

architecture Behavioral of memory_tut is
type mem is array (1023 downto 0) of std_logic_vector(15 downto 0);
signal ram : mem;
begin
process(clk)
begin
   if(clk'event and clk = '1') then
       if (we = '1') then
           ram(to_integer(unsigned((addr)))) <= din;
       end if;
       if (oe = '1') then
           dout <= ram(to_integer(unsigned((addr))));
       end if;     
end if;
end process;
end Behavioral;