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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( clk,start : in STD_LOGIC;
           ledout : out STD_LOGIC);
end top;

architecture Behavioral of top is
signal temp : std_logic := '0';
signal count : integer range 0 to 10000001 := 0;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(start = '0') then
   temp <= '0';
else
   if(count < 10000000) then
      count <= count + 1;
    else
      count <= 0;
      temp <= not temp;
   end if;
end if;
end if;
end process;

ledout <= temp;

end Behavioral;