library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;


entity top is
    Port ( clk,rst : in STD_LOGIC;
           dout : out STD_LOGIC_VECTOR (3 downto 0));
end top;

architecture Behavioral of top is
signal temp : std_logic_vector(3 downto 0) := "0000";
begin
process(clk)
begin
 if(rising_edge(clk)) then
        if(rst = '1') then
         temp <= "0000";
        else
          temp <= temp + 1;
        end if;
end if;
end process;

dout <= temp;

end Behavioral;