library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb2 is
end tb2;

architecture Behavioral of tb2 is
component top is
    Port ( clk : in STD_LOGIC;
    din : in std_logic;
    dout : out std_logic;
    reset : in std_logic
    );
end component;

signal    clk : STD_LOGIC:= '0';
signal    din : std_logic :='0';
signal    dout : std_logic;
signal    reset : std_logic := '0';



begin

T1 : top port map(clk => clk,din => din,dout => dout,reset=> reset);

p1 : process
begin
clk <= not clk;
wait for 5 ns;
end process;


--din <= '1' after 9 ns, '0' after 19 ns, '1' after 29 ns, '0' after 39 ns, '1' after 49 ns;


--p2:process
--begin
--din <= not din; 
--wait for 10 ns;
--end process;

p2:process
begin
wait for 10 ns;
din <= '1';
wait for 10 ns;
din <= '0';
wait for 10 ns;
din <= '1';
wait for 10 ns;
din <= '0';
wait for 10 ns;
din <= '1';
wait for 10 ns;
din <= '0';
wait for 10 ns;
din <= '1';
wait for 10 ns;
din <= '0';
wait for 10 ns;
wait;
end process;
end Behavioral;