library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fsm is
    Port ( clk,rst,din : in STD_LOGIC;
           dout : out STD_LOGIC);
end fsm;

architecture Behavioral of fsm is
type state_type is (s0, s1);
signal state : state_type := s0;
begin

--1) Reset logic - Sequential Process
--2) Next State, Output Logic - COmbinational Process

reset_logic: process(clk)
begin
if(rising_edge(clk)) then
   if(rst = '1') then
    state <= s0;
    else
   case(state) is
   when s0 => 
        if(din = '1') then
        state <= s1;
        dout <= '0';
        else
        state <= s0;
        dout <= '0';
        end if;
   
   when s1 =>
       if(din = '1') then
        state <= s0;
        dout <= '1';
        else
        state <= s1;
        dout <= '0';
        end if;
    when others =>
        state <= s0;
        dout <= '0';
  end case;
 end if;
end if;    
end process;

end Behavioral;