WEBVTT 00:01.370 --> 00:11.780 Welcome to module 7.2 Quartus quarters two quarters to is all Taro's tool for programming Altera FPGA. 00:11.800 --> 00:15.700 Is this too will only work for Altera FPGA. 00:15.980 --> 00:20.280 We will not be using this tool to program the basis to board. 00:20.300 --> 00:26.630 However if you have an Altera development board you'll need to follow this guide for programming your 00:26.630 --> 00:30.390 development board creating a new project. 00:30.470 --> 00:37.890 Click on the new project wizard navigate to the folder where your VHDL files are located under the directory 00:38.000 --> 00:46.220 for this project and know what is the name of this project dialog box and or the name of your VHDL design 00:46.220 --> 00:47.090 entity. 00:47.180 --> 00:49.370 Click next. 00:49.370 --> 00:50.800 Adding files. 00:50.870 --> 00:56.020 This is where we want to add all the VHDL files included in your design. 00:56.030 --> 01:01.350 Make sure to know that you will not be adding the testbench file. 01:01.430 --> 01:03.120 Select your device. 01:03.170 --> 01:09.080 Next you will want to select the device you're wanting to program you should be able to find the device 01:09.080 --> 01:18.240 family and part number located in the User Guide or data sheet click Finish project you have just created 01:18.240 --> 01:25.140 a project and Courtice you should see the VHDL design file located in the project navigator. 01:25.140 --> 01:34.660 Double click on the design file and you should see the VHDL code appear as shown on your screen compilation. 01:34.710 --> 01:38.400 The next step is to compile the VHDL design. 01:38.400 --> 01:41.660 Click processing start compilation. 01:41.940 --> 01:44.300 This should take a few minutes to complete. 01:44.430 --> 01:50.460 If there are any errors in your design you should see them show up in the system output below. 01:50.460 --> 01:56.450 Once this is completed you will see a compilation report IO routing. 01:56.580 --> 02:04.340 The next step is to link the FPGA pends to the VHDL design entities inputs and outputs. 02:04.350 --> 02:07.050 This is done by clicking on assignments. 02:07.110 --> 02:10.640 Pin planner IO routing. 02:10.770 --> 02:15.990 This will bring up the pin planner tool it should look something like what you see on your screen. 02:16.350 --> 02:18.390 Once you have mapped all the pins. 02:18.390 --> 02:20.030 Select File Save. 02:20.340 --> 02:29.070 Then exit out of the pin planner recompile ation the next step is to recompile the VHDL design click 02:29.070 --> 02:32.280 processing start compilation. 02:32.280 --> 02:34.570 This may take a few minutes to complete. 02:34.830 --> 02:40.600 If there are any errors in your design you should see them show up in the system output below. 02:40.620 --> 02:49.240 Once this is completed you will see a compilation report that includes the number of pins used programmed 02:49.300 --> 02:50.600 device. 02:50.610 --> 02:52.170 Now click on Tools. 02:52.170 --> 02:53.150 Programmer. 02:53.400 --> 02:59.540 This will bring up a new screen where you will have to select the type of programmer you are using. 02:59.550 --> 03:01.560 This will vary board the board. 03:01.650 --> 03:10.860 Next select Add file you want to navigate to the projects directory and find a dot file. 03:11.070 --> 03:15.150 The file name will be the same name as your Courtice project. 03:15.150 --> 03:20.990 Then click on upload and the FPGA should be configured with your file. 03:21.000 --> 03:27.660 Now it's very important to remember that if you power off your board the FPGA will lose its configuration 03:28.020 --> 03:29.940 and you will have to reprogram it. 03:30.150 --> 03:37.200 If your development board contains a flash chip you can load the dot S-O file onto it so that every 03:37.200 --> 03:41.330 time you power on the board your program will run. 03:41.450 --> 03:45.830 We have just completed modules 7.2 quarters too. 03:46.070 --> 03:48.560 Here's a summary of everything we went over. 03:48.740 --> 03:50.560 Use this module as a reference. 03:50.600 --> 03:57.440 If you have an Altera board you're wanting to program all of the designs utilize and the labs will work 03:57.530 --> 04:00.010 and run on an Altera development board.