WEBVTT 00:01.230 --> 00:11.610 Welcome the module 7.1 model asem model some model Semb is an extremely powerful tool set that is used 00:11.610 --> 00:20.370 to simulate and test your VHDL designs all the labs include Moulson screenshot showing you what the 00:20.370 --> 00:23.110 output of your design should look like. 00:23.130 --> 00:26.720 You can code your VHDL design inside a model. 00:27.060 --> 00:36.810 However I prefer to use notepad plus plus which is a free tool that allows you to edit VHDL files simulation 00:36.810 --> 00:37.800 steps. 00:37.820 --> 00:43.620 Here is a list of all the simulation steps to create project and models. 00:44.100 --> 00:50.970 I would suggest to use this as a reference to simulate the VHDL designs in the labs. 00:50.970 --> 00:55.950 Step one is to create all necessary VHDL files. 00:55.950 --> 01:00.760 Step two is to navigate to your VHDL design directory. 01:00.960 --> 01:05.210 Step three is to create a model SCM library. 01:05.220 --> 01:08.930 Step 4 is to compile and simulate your design. 01:10.300 --> 01:18.240 The first step is to create all the necessary files which includes one the design file. 01:18.340 --> 01:26.320 This is the file that contains your VHDL design to the test bench file which I will be providing for 01:26.320 --> 01:27.180 you. 01:27.330 --> 01:28.220 3. 01:28.360 --> 01:33.450 The TCM script I will be providing this for you as well. 01:33.550 --> 01:42.760 When organizing your VHDL designs I suggest organizing them as shown in the image on the right opening 01:42.760 --> 01:43.590 model. 01:43.990 --> 01:49.580 Now fire up model sim and your screen should look something like this. 01:49.690 --> 01:52.660 Step Two change directory. 01:52.660 --> 02:00.850 Step 2 is to click on File change directory and then navigate to the folder where your VHDL code is 02:00.850 --> 02:02.230 located. 02:02.230 --> 02:07.130 Note that you will have to do this every time you open Moulson. 02:07.330 --> 02:10.190 Step 3 create a library. 02:10.360 --> 02:13.690 The next step is to create a model some library. 02:13.930 --> 02:21.890 Every time you navigate to a new directory you will have to create a model some library in order to 02:21.890 --> 02:32.420 create a massive library click on File new new library the default library name for Moulson is work. 02:32.480 --> 02:43.440 Make sure that a new library and logical mapping to it is selected step for compile the next step is 02:43.440 --> 02:47.490 to compile the VHDL design in order to do that. 02:47.490 --> 02:55.080 You need to quit compile compile and then select your VHDL design and test files. 02:55.200 --> 03:00.780 Any errors located in your VHDL design will show up in the transcript window. 03:02.160 --> 03:10.110 Step Five simulate the next step is to simulate your design in order to do this you must expand the 03:10.110 --> 03:12.630 work library and the library window. 03:13.080 --> 03:17.490 Then double click on the test bench VHDL entity. 03:17.490 --> 03:21.010 This will launch the model sim simulation window. 03:21.810 --> 03:32.360 In this sim default window right click on the dev two test or Yuichi instance and navigate to add to 03:32.810 --> 03:35.490 waive all items in region. 03:35.840 --> 03:44.810 The final step is to type run in however long you want your design to run for Step Five simulate. 03:45.070 --> 03:51.290 Here's a screenshot showing how to add all items to the simulation window. 03:51.300 --> 04:01.710 Step 4 and 5 you can combine steps 4 and 5 into one easy step with the use of a DCL script HECS script 04:01.920 --> 04:08.290 stands for tool command line which is a set of instructions that tell us what to do. 04:08.610 --> 04:16.060 I will provide you with all the TC scripts needed to complete the labs step 4 and 5. 04:16.070 --> 04:21.860 Here is a screenshot showing you how to navigate to run a TCO file. 04:23.400 --> 04:24.860 Tips and Tricks. 04:24.900 --> 04:29.090 Here's a little tip to use after your simulation has completed. 04:29.100 --> 04:32.780 Right click on the simulation window and select zoom full. 04:32.850 --> 04:38.370 This will evilest base the signals so you can see the entire simulation. 04:38.370 --> 04:44.820 Tips and Tricks here are a few tips and tricks that I feel make reading the simulation easier. 04:44.940 --> 04:50.910 If you have any other questions click on the help and then select the PTF documentation and there is 04:50.910 --> 04:54.370 a list of help documents at your disposal. 04:55.510 --> 05:01.240 Also there are many forums online that if you search you can find a lot of the information you are looking 05:01.240 --> 05:01.890 for. 05:02.170 --> 05:05.410 If you're having troubles you cannot figure out. 05:05.440 --> 05:10.350 Feel free to send me an email and I will do my best to help you. 05:10.360 --> 05:13.620 We have just finished Marjoe 7.1 Moulson. 05:13.840 --> 05:16.690 Here's a summary of some of the things we went over. 05:16.720 --> 05:20.110 You need to have a model library for every project. 05:20.110 --> 05:25.450 You cannot manually compile he or you can manually compile and simulate your designs. 05:25.450 --> 05:31.570 However using a typical scripts are a much easier and faster way of simulating.